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DRA80M: Hyperflash CFI area

John H. Gardner
Mastermind 33981 points

Part Number: DRA80M

A customer noted the following to me: In 12.3.3.5.1.1 Hyperflash Access Sequence Table 12-6892 of TRM for Maxwell SPRUIE8C it is mentioned (under step 1):

- Issue a few (16 to 20) reads to the HyperFlash CFI region and ensure that the 'Manufacture ID' and/or the "Device ID"
registers in the Flash can be accessed correctly. The ID values read from the Flash can be compared with the expected
value from the manufacturer’s datasheet. Reading the correct value from the Flash ensures that the MDLL has achieved
lock.

Could you please let me know where is CFI region for Hyperflash? (from both R5F and A53 memory view)

  • 0
    TI__Genius 15120 points

    Hi John,

    CFI region is a function embedded in the Flash memory and defined by JEDEC.

    You can refer to the flash memory datasheet for Device ID and CFI mode entry.

    An example from a random flash datasheet (FYI):

    The system can access the ID-CFI ASO (Address Space Overlays) by issuing the ID-CFI Entry command sequence during Read Mode. This entry command
    uses the Sector Address (SA) in the command to determine which sector will be overlaid.

    The ID-CFI ASO allows the following activities:
     -  Read ID-CFI ASO, using the same SA as used in the Entry command.
     -  ASO Exit.
    The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Low Level Driver User Guide for
    general information on Cypress flash memory software development guidelines.
    /* Example: CFI Entry command */
    *( (UINT16 *)base_addr + 0x555 ) = 0x0098; /* write CFI entry command */
    /* Example: CFI Exit command */
    *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* write cfi exit command */

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Expert 2750 points

    Hi Stan,

    Thank you for the response.

    What I mean is where exactly in the CPU memory map of J7 the CFI base is located. (both R- and A- cores)

    From you code example:

    *( (UINT16 *)base_addr + 0x555 ) = 0x0098; /* write CFI entry command */     // <----- what should be the value of base_addr in Jacinto memory map?

    E.g. at which address does Jacinto map the CFI buffer of the flash device.

    Thank you in advance for the assistance.

    Best regards,

    Vladimir

  • 0 in reply to Vladimir Z
    TI__Genius 15120 points

    Hi Vladimir,

    It is important to understand that CFI buffer is not mapped by J7 in any way. The CFI access is internal function to the Hyper flash memory itself. CFI buffer can be overlaid to any flash sector of the flash memory with the code example above.

    The J7 memory map which is related to the FSS DATA REGION (FSS is the J7 flash controller for OSPI + hyperflash) can be found in the TRM section 2.2 MCU Domain Memory Map:

    MCU_FSS0_DAT_REG1  0x0050000000 0x0057FFFFFF  128 MB

    MCU_FSS0_DAT_REG0  0x0400000000 0x04FFFFFFFF  4 GB
    MCU_FSS0_DAT_REG3  0x0500000000 0x05FFFFFFFF  4 GB

    For FSS regions 1-3 usage, please refer to TRM section 12.3.1.4.6 FSS0 and FSS1 Regions

    regards,

    Stan