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K2GICE: PCI-e MSI Hwi interupts

Intellectual 640 points

Replies: 18

Views: 195

Part Number: K2GICE

Hi

Im trying to figure out how to enable MSI interupts to my code. I feel like i have pretty ok understanding of what i have to do after reading Creating Hwi objects from here http://www.ti.com/lit/ug/spruex3t/spruex3t.pdf and Interupt support from here http://www.ti.com/lit/ug/sprugs6d/sprugs6d.pdf . I anyhow wasnt abble to find information how to translate pciess interupt event number to interupt number (id) needed on creating hwi object. How does this step work.

Im using k2gIce as an rc and fpga as ep. Link has been tested and memory writes and reads work.

-Tommi Mehtonen

  • Hi, Tommi,

    Is the PCIe RC configured by ARM or DSP? and if ARM, is it using Linux or RTOS?

    Rex

     

  • In reply to Rex Chang:

    Hi

    PCIe RC is configured by DSP and RTOS. Arm is not used at all in this configuration.

    Tommi

  • In reply to Tommi Mehtonen:

    Hi, Tommi,

    Got you. I'll have DSP PCIe expert to help you.

    Rex

     

  • Guru 80515 points

    In reply to Rex Chang:

    Hi,

    From K2G TRM, Table 9-53. CIC Input Events Mapping, those are the PCIE system event number:

    224 PCIE_INT0 PCIe interrupt 0
    225 PCIE_INT1 PCIe interrupt 1
    226 PCIE_INT2 PCIe interrupt 2
    227 PCIE_INT3 PCIe interrupt 3
    228 PCIE_INT4 PCIe interrupt 4
    229 PCIE_INT5 PCIe interrupt 5
    230 PCIE_INT6 PCIe interrupt 6
    231 PCIE_INT7 PCIe interrupt 7
    232 PCIE_INT8 PCIe interrupt 8
    233 PCIE_INT9 PCIe interrupt 9
    234 PCIE_INT10 PCIe interrupt 10
    235 PCIE_INT11 PCIe interrupt 11
    236 PCIE_INT12 PCIe interrupt 12
    237 PCIE_INT13 PCIe interrupt 13

    For PCIE user guide: 

    0 PCIe express legacy interrupt mode - INTA (RC mode only)
    1 PCIe express legacy interrupt mode - INTB (RC mode only)
    2 PCIe express legacy interrupt mode - INTC (RC mode only)
    3 PCIe express legacy interrupt mode - INTD (RC mode only)
    4 MSI interrupts 0, 8, 16, 24 (EP/RC modes)
    5 MSI interrupts 1, 9, 17, 25 (EP/RC modes)
    6 MSI interrupts 2, 10, 18, 26 (EP/RC modes)
    7 MSI interrupts 3, 11, 19, 27 (EP/RC modes)
    8 MSI Interrupts 4, 12, 20, 28 (EP/RC modes)
    9 MSI Interrupts 5, 13, 21, 29 (EP/RC modes)
    10 MSI Interrupts 6, 14, 22, 30 (EP/RC modes)
    11 MSI Interrupts 7, 15, 23, 31 (EP/RC modes)
    12 Error Interrupts
    [0] System error (OR of fatal, nonfatal, correctable errors) (RC mode only)
    [1] PCIe fatal error (RC mode only)
    [2] PCIe non-fatal error (RC mode only)
    [3] PCIe correctable error (RC mode only)
    [4] AXI Error due to fatal condition in AXI bridge (EP/RC modes)
    [5] PCIe advanced error (RC mode only)
    13 Power management and reset event interrupts
    [0] Power management turn-off message interrupt (EP mode only)
    [1] Power management ack message interrupt (RC mode only)
    [2] Power management event interrupt (RC mode only)
    [3] Link request reset interrupt (hot reset or link down) (RC mode only)

    If you want to use MSI-0, you need PCIE_INT4, that is system event 228. To configure HWI, you may refer to how we did for DDR ECC interrupt on K2G, where system event is 198 (DDR3_ERR EMIF error interrupt). The code is under pdk_k2g_1_0_xx\packages\ti\csl\example\ecc\ecc_test_app. There is 1-bit ECC ISR function isrEmifSecErr(), you can trace back how this ISR is setup and registered.

    Regards, Eric

  • In reply to lding:

    Hi

    I looked around examples but i keep sunning on problem when creating the hwi. Im using modified pcie example as an base and i am trying to create the interupt after setting upt the link and testing it with following code:

          Hwi_Handle hwi0;
          Hwi_Params hwiParams;
          Error_Block eb;
          Error_init(&eb);
          Hwi_Params_init(&hwiParams);
          hwiParams.arg = 5;
    
          hwi0 = Hwi_create(1, pcie_reader, &hwiParams, &eb);
          Hwi_eventMap(1, 17);
    
          if (hwi0 == NULL) {
           System_abort("Hwi create failed");
          }
          PCIE_logPrintf("Hwi done \n");

    event number 17 is based on chapter 6.2.2.1 DSP Interrupt Sources on 66ak2gx's trm. Code compiles, but on creation i get following error message:

    ti.sysbios.family.c64p.Hwi: line 189: E_invalidIntNum: Invalid interrupt number: intr# 1
    Hwi create failed

    I also get warning:

    Description Resource Path Location Type
    #169-D argument of type "void (*)(void)" is incompatible with parameter of type "ti_sysbios_interfaces_IHwi_FuncPtr" pcie_sample.c /DSP_pcie_platform line 1178 C/C++ Problem

    for Hwi_create line.

    Same error occurs if i try to make the interrupt on main before BIOS_start()

    My includes are:

    #include "pcie_sample.h"
    #include <ti/drv/pcie/soc/pcie_soc.h>
    #include <stdint.h>
    #include "ti/board/board.h"
    #include <ti/csl/csl_bootcfgAux.h>
    #include <ti/csl/csl_xmcAux.h>
    #include <ti/csl/csl_serdes_pcie.h>
    #include <ti/csl/csl_pscAux.h>
    #define PCIE_REV0_HW
    #include <ti/csl/csl_cacheAux.h>
    #include <ti/csl/csl_chip.h>
    #include <ti/sysbios/knl/Clock.h>
    #include <ti/sysbios/timers/timer64/Timer.h>
    #include <xdc/runtime/Error.h>
    
    and on pcie_sample.h
    
    /* C Standard library include */
    #include <string.h>
    
    /* XDC include */
    #include <xdc/std.h>
    #include <xdc/runtime/System.h>
    
    /* BIOS include */
    #include <ti/sysbios/BIOS.h>
    #include <ti/sysbios/knl/Task.h>
    #include <ti/sysbios/family/c64p/EventCombiner.h>
    #include <ti/sysbios/family/c64p/Hwi.h>
    #include <ti/sysbios/knl/Event.h>
    
    /* CSL include */
    #include <ti/csl/cslr_device.h>
    
    /* PCIE LLD include */
    #include <ti/drv/pcie/pcie.h>
    
    #include "PCIeEDMA.h"
    #include <xdc/runtime/System.h>
    #include <ti/drv/uart/UART_stdio.h>
    

  • Guru 80515 points

    In reply to Tommi Mehtonen:

    Hi,

    ti.sysbios.family.c64p.Hwi: line 189: E_invalidIntNum: Invalid interrupt number: intr# 1 =======> Please try to use an interrupt number between 4 and 15 (inclusive) for this.

    Regards, Eric

  • In reply to lding:

    Hi

    Got the interupt done with intNum 8:

      Hwi_Handle hwi0;
      Hwi_Params hwiParams;
      Error_Block eb;
      Error_init(&eb);
      Hwi_Params_init(&hwiParams);
      hwiParams.arg = 5;
    
      hwi0 = Hwi_create(8, pcie_reader, &hwiParams, &eb);
      Hwi_eventMap(8, 228);
    
      if (hwi0 == NULL) {
       System_abort("Hwi create failed");
      }
      PCIE_logPrintf("Hwi done \n");
    
    
    
      BIOS_start();

    I tried eventmap() with both 228 and 17. On ROV it shows:

    Should the eventId/Eventbumber be visible there.

    -Tommi

  • In reply to Tommi Mehtonen:

    Hi

    Had time to work on this one again and found the page https://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices. I added line "  hwiParams.eventId = 17; which seems to do the trick as i got timer interups working from that one using the table http://www.ti.com/lit/ug/spruhy8i/spruhy8i.pdf page 626.

    Anyhow MSI interupt itself does not seem to work. Im not sure if the problem is on dsp or fpga side. Is there need to enable MSI interupts for pcie separately or are those enabled automatically.

    -Tommi

  • In reply to Tommi Mehtonen:

    answering to myself yes, by writing the register MSI0_IRQ_ENABLE_SET 

  • In reply to Tommi Mehtonen:

    Hi

    Now iv have gotten my interupts working when in manyally write 1 to register PCIE_APPLICATION_PVIE_MSI0_IRQ_STATUS_RAW (0x21800100). Anyhow interrupts form the fpga dont come thought. Im thinking that this would be memory translation problem.

    What thse value should be on the pcie_sample.h and is there any other memory translation registers i should set up or way of debugging this situation.

    /* Inbound Base Address for PCIe RC */
    #define PCIE_IB_LO_ADDR_RC 0x21800100
    #define PCIE_IB_HI_ADDR_RC 0

    /* PCIE address space for MSI */
    #define PCIE_PCIE_MSI_BASE (0x00000000U)
    #define PCIE_PCIE_MSI_OFF (0x00000000U)

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