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Original question:

DRA80M: Access to WKUP_GPIO via MCU and Main domain

AM6548: Access to WKUP_I2C0 from MCU domain (R5)

Daisuke Maeda
Guru 19845 points
Part Number: AM6548
Other Parts Discussed in Thread: TMDX654IDKEVM, TPS62363

Our customer wants to know how to access WKUP_I2C0 for controlling the MPU voltage regulator in the bootloader on R5 because the current PSDK RTOS does not support controlling the TPS62363 regulator for TMDX654IDKEVM.

http://e2e.ti.com/support/processors/f/791/t/886041

In the previous related thread, it is answered that R5 has full accessibility of everything memory mapped on the SoC level, except its own ATCB/BTCM .

Can R5 direct access to WKUP_I2C0_CFG region address?

WKUP_I2C0_CFG region address: 0x0042120000 - 0x00421200FF

From the software perspective, are the only differences between WKUP_I2C0, MCU_I2C0, and MAIN I2C their addresses?

Our customer will modify the source code for MAIN I2C to apply to WKUP_I2C0.

Best regards,

Daisuke

  • 0
    TI__Genius 14680 points

    Daisuke-san,

    Can you please clarify your reference to the R5F access to its local TCM?

    For the I2C question,  yes the R5F CPUs are able to access the WKUPSS I2C. See Table 3-16 of the TRM: WKUP_CBASS0 Connectivity Matrix.

    The I2C differences are mentioned in section 12.1.3.1 of the TRM:

    The WKUP_I2C0 and MCU_I2C0 controllers have dedicated I2C compliant open drain buffers, and support fast mode (up to 400 Kbps).The I2C0, I2C1, I2C2, and I2C3 controllers are multiplexed with standard LVCMOS I/O and connected to emulate open drain.The I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1.

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Guru 19845 points

    Hi Dave-san,

    Thank you for your reply.

    Dave Bell said:

    For the I2C question,  yes the R5F CPUs are able to access the WKUPSS I2C. See Table 3-16 of the TRM: WKUP_CBASS0 Connectivity Matrix.

    I checked the WKUP_CBASS0 Connectivity Matrix. There is no connection between MCU_ARMSS0_P0 or MCU_ARMSS0_P1 and WKUP_I2C0.

    Is my understanding incorrect?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Genius 14680 points

    Daisuke-san,

    The access is through the RD and WR ports from the R5. There are three interfaces to the system, described in section 6.3:

    6.3.3.3 MCU_ARMSS Interfaces

    6.3.3.3.1 Master Interfaces
    The MCU_ARMSS has two master interfaces per CPU:
    • 64-bit VBUSM master pair (1 read, 1 write) for L3 memory accesses; this is the main memory interface
    – Includes region-based address translation (RAT)
    • 32-bit VBUSP master for peripheral access
    – Includes logic that provides the R5F CPU with a private access to VIM and RAT
    – Enabled at reset

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Guru 19845 points

    Hi Dave-san,

    Thank you for your reply.

    I understand as follows:

    MCU_ARMSS0_Px:  32-bit VBUSP master for peripheral access
    MCU_ARMSS0_DBG_RDx: 64-bit VBUSM master for L3 memory read
    MCU_ARMSS0_DBG_WRx: 64-bit VBUSM master for L3 memory write

    Our customer will refer to the source code for J721E SoC to access WKUP_I2C0 for controlling the MPU voltage regulator in the bootloader on R5.

    Best regards,

    Daisuke