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OMAPL138B-EP: Current setting for priority between CPU/IDMA/SDMA

Intellectual 460 points

Replies: 1

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Part Number: OMAPL138B-EP

Hi

I want to check  Current setting for priority between CPU/IDMA/SDMA and may be need to change this as well.

HOw do I check and change priority ?

Is there any SFR available for it?

Following are the silicon errata(Ref:-Silicon errata sprz301m) in which it is mentioned about priority issue because of this I want to check priorities

Advisory 2.3.1 DMA Access to L2 RAM Can Stall When DMA and C674x CPU Command Priorities
Are Equal

Note: DMA refers to all non-CPU requests. This includes Internal Direct Memory Access
(IDMA) requests and all other system DMA master requests via the Slave Direct Memory
Access (SDMA) port.
The C674x Megamodule uses a bandwidth management (BWM) system to arbitrate
between DMA and CPU requests issued to L2 RAM. See TMS320C674x DSP
Megamodule Reference Guide, Literature Number - SPRUFK5 for more information on
the BWM. BWM arbitration grants L2 bandwidth based on programmable priorities and
contention- cycle-counters. The contention-cycle-counters count the number of cycles for
which the associated L2 requests are blocked by higher priority requests. When the
contention-cycle-counter reaches a programmed threshold (MAXWAIT), the associated
L2 request is granted a slice of L2 bandwidth. This prevents indefinite blocking of low
priority requests when faced with the continuous presence of higher priority requests.
Ideally, the BWM arbitration will grant equal L2 bandwidth between equal priority DMA
and CPU requests. Instead, when equal priority DMA and CPU requests arrive at the
BWM, bandwidth is always granted in favor of the CPU over DMA. In the case of
successive CPU requests, it is possible for the CPU to block all DMA requests until CPU
traffic subsides. Additionally, some command logic in the BWM uses priority level 7,
which can also result in SDMA stalls when the CPU is also programmed to priority level
7. 

Regards,

Satheesh

  • Hi Satheesh,

    This is covered in Chapter 6 - Bandwidth Management Architecture of the TMS320C674x DSP Megamodule Reference Guide.

    The Bandwidth Management (BWM) system arbitrates DMA and CPU requests to L2 RAM. If equal priority requests come from both the DMA and CPU at the same time, the BWM will always give access to the CPU first. This can cause the DMA to stall until CPU requests are complete.

    If you suspect this is an issue in your system, you can modify the priority of the CPU and DMA. You can also specify the maximum time allowed for the CPU or DMA to wait on a request. Once this time is reached, the requester will be given a priority level of -1, indicating highest priority, and will be allowed to complete a transfer. 

    Default priorities and max wait times are specified in Table 6-3 in the Megamodule Reference Guide linked above.

    Regards,
    Sahin


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