DRA71XEVM: LVDS Out can not get VOUT2 Clock

fanok

Part Number: DRA71XEVM
Other Parts Discussed in Thread: TIDEP-01002, DRA722, DS90C189-Q1

Hi all experts,

my custom board is based on the TIDEP-01002 EVM board, and SOC is dra722_es, Kernel version is 4.14. my LCD video path is :

SOC -> VOUT2 -> DS90C189-Q1 -> LCD.

GPIO pinmux as following:

vout2_clk is vin2a_fld0 pinmux to M4. the others pinmux be config in mux_data.h in uboot.

i also use omapconf to check the register of CTRL_CORE_PAD_VIN2A_FLD0, the value is 0x000010004, it is correct.

but use oscilloscope to check VOUT2_CLK pin, it is not working. VOUT2_D0~VOUT2_D24 have digital signal. so there is nothing show on the screen.

could any one help me figure out the problem?

best regards!

over 4 years ago

0 fanok over 4 years ago

Expert 2400 points

append DSS registers info:

[root@x ~]# /home/debug_dss_clockdumps.sh

=====================DSS clock script===================
Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x0000028E
video1 PLL : Enabled
video2 PLL : Disabled
HDMI PLL : Disabled
DSI1_A_CLK mux : DPLL HDMI
DSI1_B_CLK mux : DPLL Video1
DSI1_C_CLK mux : DPLL Video1

DSS_CTRL (0x58000040) = 0x00001000
2: LCD1 clk switch : DSS clk
3: LCD2 clk switch : DSI1_B_CLK
10: LCD3 clk switch : DSS clk
1: func clk switch : DSS clk
13: DPI1 output : HDMI

DSS_STATUS (0x5800005C) = 0x01409281

DSI_CLK_CTRL (0x58004054) = 0x80004001

CM_DSS_CLKSTCTRL (0x4A009100) = 0x00000703

CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00001102

========================================================
Register dump for DPLL video1
Warning: chip not recognized, running in safe mode (only platform-generic functions allowed).

|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58004300    | 0x00000018 |
| 0x58004304    | 0x00002603 |
| 0x58004308    | 0x00000000 |
| 0x5800430C    | 0x000C784A |
| 0x58004310    | 0x00E06008 |
| 0x58004314    | 0x00000008 |
| 0x58004318    | 0x00000000 |
| 0x5800431C    | 0x00000000 |
| 0x58004320    | 0x00000000 |
|----------------------------|

Details for DPLL video1
PLL status : Locked
M4 hsdiv(1) : inactive
M5 hsdiv(2) : inactive
M6 hsdiv(3) : Active
M7 hsdiv(4) : inactive

PLL_REGM   = 1596
PLL_REGN   = 37
M4 DIV     = 0
M6 DIV     = 8
M7 DIV     = 0

Clock calculations (DPLL video1)
sysclk = 20000000
DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1680000000
M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 0
M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 186666666
M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0

========================================================
Clock O/P of MUXes
/home/debug_dss_clockdumps.sh: line 309: arithmetic syntax error
[root@x ~]# update frame 1000 in 16255 ms. 0 event. 0 touch.

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DRA71XEVM: LVDS Out can not get VOUT2 Clock