Hi.
I have project where FPGA would send MSI interrupt every 50 µs informing that data is ready to be processed.
Atm we are facing problem where interrupt every 800 µs works but one every 80 µs does not. On 80 µs dsp does not seem to receive even the first interrupt. It is not clear yet if the problem is on fpga or dsp. Is there limit on msi interrupt freguency on TI's hardware.
Execution analysis shows that the code run on interrupt take around 10 µs.
Best Regards
Tommi Mehtonen