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Part Number: K2GICE
I have project where FPGA would send MSI interrupt every 50 µs informing that data is ready to be processed.
Atm we are facing problem where interrupt every 800 µs works but one every 80 µs does not. On 80 µs dsp does not seem to receive even the first interrupt. It is not clear yet if the problem is on fpga or dsp. Is there limit on msi interrupt freguency on TI's hardware.
Execution analysis shows that the code run on interrupt take around 10 µs.
Please let us know the software you used on TI K2G device? Is it Processor SDK RTOS or Linux? Is it C66x receiving the MSI interrupt, not A15? Is K2G the PCIE RC? Are you easily able to use A15 to handle MSI for the same test?
We had test on TI K2H PCIE handling the MSI years ago. The test setup is K2H ---------PCIE--------K2H with ARM running 1GHz. The EP side generates the MSI interrupt at 31.25 us interval to RC, and EP also generates some background traffic at even smaller intervals, say several us with payload hundreds bytes via EDMA. We didn't have any issue for RC to receive and handle all the MSI interrupt.
K2G and K2H PCIE IP are the same (may be small variations) and it should work for 80 us MSI.
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In reply to lding:
Turns out that for some reason FPGA started sending interrupts too early. By adding delay after "user_link_up" interrupts started working and we were able to achieve desired interrupt interval.
Thanks for your info.
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