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TMS320C6678: TSIP Signals Termination

erez cohen
Intellectual 595 points
Part Number: TMS320C6678

Hello,

On SPRABI2D section 6.12.2  it is stated:

"Then a single termination can be implemented at the end of the bus to

reduce over-shoot and under-shoot, which minimizes EMI and crosstalk. This need is even more likely
whenever a TSIP bus passes through board-to-board connectors."

On my design BtB connector used , please advise what termination should be used and where it should be located.

thanks,

Erez

  • 0
    TI__Mastermind 46460 points

    Erez,

    It depends on many things.  If you want a precise, analytical answer, you will need to perform IBIS simulations.  These simulations will need to contain models for all signal sources, loads, PCBs and connectors.  You will then need to verify the signal integrity at all inputs.

    What is your topology?  Is it point-to-point or are there multiple loads (i.e. multi-drop) or even multiple drivers (i.e. TDM add-drop mux)?  A block diagram showing the drivers and loads and trace lengths and connectors would be helpful.  What is your data rate?

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    The DSP is connected point to point but thru BTB connector: the design includes a carrier with 2 DSPs on a mezzanine. DSP TSIP I/F is connected to FPGA at the rate of 16MHz.

    Erez.  

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    A point-to-point connection at 16Mbps should be fairly straightforward.  How long are the routes?  Terminations on the data and frame sync signals should not be needed.  What is the source of the clock?  Ideally, you will need to implement the clocks so that they arrive at both ends of the links at the same time.  You can do this be using a clock buffer from the clock source and then matched length routes to each DSP and to the FPGA.  A series termination resistor at the driver end of each clock route should be sufficient.  Common values are 22 or 33 ohms.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    I assume 6-8" trace length, FPGA to TSIP.

    Each DSP receives its Data and FS/CLK from FPGA , so there is no line matching problem. 

    As I wrote, FPGA drives the DSP CLK and we have a series termination. Do you recommend to move the termination to the end of the line (place it on the TSIP CLK input of the DSP)? if yes, why? Or keep two series terminations on source and also on destination (near C6678)?

    According to your answer the TSIP Rx signals (also DSP inputs), should not be terminated ? why?

    Erez.

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    Series terminators are always placed close to the transmitter.  This allows the output impedance of the buffer to better matched to the PCB trace characteristic impedance.  This dampens the signal rise time to prevent overshoots.  It also back-terminates any reflection from the high impedance loads.  Bidirectional nets sometimes have resistors at both ends since there is a driver at each end.

    The series terminations discussed above are often implemented for clock nets to prevent glitching due to overshoots and undershoots; especially on long routes like you are using.  Similar series terminations can be implemented on data routes to dampen ringing that may be a problem with EMI.

    Sourcing the clock from the FPGA is not a perfect solution.  It only accounts for delays in one direction.  A common external clock is the ideal solution.  You can mimic that when sourcing the clock from the FPGA by routing this clock out through a buffer and then back into the FPGA on a different pin along with the data and frame sync.  The clock length routed to the DSP and to the FPGA should be length (delay) matched.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    Attached is block diagram of the FPGA<-> DSP terminations. please confirm or update.

    i am not sure i understand the last paragraph. Do you mean the propagation delay between the Tx and Rx path relative to its FS may cause synchronization problems? if this is the issue we can compensate it.

    Erez.   

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    You may want to delete the attachment.  I doubt that you want that displayed on a public forum.  I assumed that you would post a block diagram only of the TSIP connections.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Erez,

    I am glad that I asked for the block diagram.  This is not a point-to-point TSIP interconnect.  As stated, this is a PCM mesh where 3 DSPs are connected to a single TSIP RX and TX and then connected to a framer at 16.384Mbps.  Additionally, the TSIP is traversing a connector to a mezzanine board containing one of the DSPs.  This presents a very challenging timing closure.  You will need a solution as shown on page 3 where the TSIP outputs are combined through an AND gate where all unused timeslots are driven high.  You will need the series resistors as drawn but the pull-up resistors to 1.8V are not required.

    Forget that last paragraph above.  I thought that the RX and TX data were going through the FPGA as well.  This clock loopback would have allowed the data to be clocked at the FPGA at the same time it is clocked at the DSP.

    Please provide more detail showing your clock and frame sync distribution.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    sorry for the inconvenience, attached is updated Block Diagram. i assume it is much reasonable.

    Erez.4834.Visio-BD_ALL.pdf 

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    This diagram shows the TX and RX TSIP streams going to the FPGA.  This is not what I saw in the other block diagrams.  They showed the TSIP links connecting from the DSPs directly to a framer.  Which implementation are you currently creating?  If it is the one with all TSIP data signals in and out of the FPGA, then taking the clock from the FPGA to a low-skew clock buffer and then driving into all connected devices with individual clocks that are delay matched may be the best solution.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    you are right! we changed the way DSPs connected to the Framers and now all DSPs and Framers connected to FPGA that performs the "PCM mesh" internally.

    my question is regarding the terminations need to be implemented on the DSP <-> FPGA. does the series terminations i added sufficient? should i add parallel terminations?

    for your convenience I added the Framers section to the BD. 

    Erez.Visio-BD.pdf

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    The series terminations should be sufficient.  You may want to add one to the FS transmitter too for improved signal integrity.  I do not think that you will need load terminations unless the route is long and inductive.  How long is the route to the mezzanine?  What type of connector are you using?

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    i am using Samtec  ERF8-050-05.0-L-DV-K-TR.

    routing length should be 8-10"

    Erez.

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    That connector has far more bandwidth than needed for TSIP.  How are you mapping the signals and grounds in the connector?  I do not see a ground blade in the center of the connector like many of their other connectors.  Will you be using a GSSGSSG pattern or even a GSGSG mapping?  I recommend that you use one of these to optimize signal integrity.

    The 8-10" routing length will add 1.5 to 2ns of signal delay.  This will need to accounted in your timing closure.

    I believe the series terminations on the signals near the transmitters will be sufficient.

    Since all of the questions have been answered, I will close this thread.  If you have further questions about this topic, you can still post to this thread.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    attached is the connector signals mapping.DSP CONNECTOR.pdf 

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    That looks reasonable.

    Tom