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TMS320C6678: EDMA multiple channels increase the latency of timer interrupt

Shine
Genius 13655 points
Part Number: TMS320C6678

Hello Champs,

When customer used multiple EDMA channels simutaneously, he found it influenced the latency of timer interrupt. 


He configured a global timer interrupt and used TSCL in ISR to calculate the cycles. The multiple channels are from different TC. The latency of timer interrupt is related with the EDMA data throughput. He also changed the priority through QUEPRI register, but the result is the same. Besides, he found when EDMA access EMIF memory, it didn't influence the timer latency. When EDMA access PCIe, L2 or DDR3 memory, the latency will increase from 500ns to 3us. How to improve the latency. 

Thanks.
Rgds

Shine

  • 0
    TI__Guru* 95265 points

    Hi,

    Do you have the information what timer is used and if change the timer instance number helps? Also, will the EDMA generate an interrupt when submitting or completing the transfer? And if there is EDMA ISR and caused the timer ISR delay? And what vectID (INT 4 to 15) is used for the timer ISR and EDMA ISR? INT4 has the highest priority and INT15 has the lowest. Is EDMA interrupt priority lower than timer? Is possible to disable the EDMA ISR in the IER bit? 

    Also, you may look into the interconnect information to understanding any bottleneck. See the C6678 datasheet. Chapter 4, like how timer, EDMA CCx/TCx, EMIF, PCIE, DDR3, L2 are connected in the fabric.

    Regards, Eric

  • 0 in reply to lding
    Prodigy 10 points

    Hi,

    1.We used the Timer 8,the global timer

    2.We did not config the EDMA completing interrupt

    3.INT4 for the timer ISR

    4.Can EDMA access the fabric disable the interrupt?

  • 0 in reply to user4832737
    TI__Guru* 95265 points

    Hi,

    He configured a global timer interrupt and used TSCL in ISR to calculate the cycles. .... the latency will increase from 500ns to 3us======>I want to confirm you what you mean the latency of the timer interrupt is delayed. 

    Let's say timer 8 is a periodic timer, at the entering point of the timer ISR you record the TSCL as T1, and at the end of the ISR you record another TSCL as T2. Given the interrupt is fired multiple times, you can collected an array of T1 and T2.

    Without any EDMA traffic, if you do a delta between T1, you should expect it is the same as timer period. T2 - T1 is the time to process ISR also should be little variations.

    When you have EDMA traffic causing the delay, do you mean the delta T1 increased? It only increased for the first one, but then constant at  the timer period for the rest? It means the interrupt latency got longer, but still keep up with the timer interrupt. 

    Or, you have a scope attached to timer pin and inside the ISR you toggle a GPIO pin, then you measure the latency when a timer rising/failing edge to GPIO edge to calculate the latency (this is unlikely your case).

    Please explain how do you use TSCL to infer the latency is increased.

    Regards, Eric 

  • 0 in reply to lding
    TI__Guru* 95265 points

    Any update?

    Eric