TMS320C6678: Clarification required for DDR3 single ended trace impedance

Hi Bill,

It would have been more effective if your point that  - "for address lines, 40 ohm trace impedance is ideal (for a 40 ohm fly-by parallel termination) and that 50 ohm was a trade-off for real state," was mentioned in the DDR3 appnote. Then, designers would make the choice themselves.As of now, from the appnote, it sounds kind of mandatory to route address lines with 50 ohms trace impedance.

For example, we are already planning to route DDR3 address lines to 40 ohms for some other device on the same board. Based on appnote, we may think that for TI DSP DDR3 interface, we have to route address lines with 50 ohms trace impedance and then terminate them on 40 ohms (already a 10 ohms impedance difference introduced by design, and we haven't considered the tolerance yet!).

Thanks and Regards,

Binayak

Hi Binayak,

Unfortunately, neither answer is completely accurate.  For more information I suggest you take a look at the JEDEC specification for the DDR4 UDIMM module.  It includes a section on trace impedance targets which specifies the difference between the routing in the lead-in section before the first DDR device and the loaded section between the first device and the termination.  You will find that the lower termination is ideal for the lead-in section of routing but that 50 ohm is used for the loaded section.  Ideally, simulation should be used to identify the best possible impedance for your design but we settled on suggesting 50 ohm since the lead-in for embedded systems is generally shorter than for UDIMMs. Simulation to set the trace impedance and check the performance at each device is the best way to determine the actual needs for your system.

Regards, Bill

Hi Binayak,

Did you have any other questions?

Regards, Bill

Dear Bill,

Sorry for the delay. I was going through some literature regarding the same issue. My response is little long, so please bear with me.

I went through the document you had referred.

As per the TI appnote (SPRABI1C), KeyStone-I device will present a 45-Ω output impedance when driving CAC signals. I am using the VTT terminating resistor of 39 ohms.

First I modified the definition of lead-in section because I'm not using DIMMs (I am mounting 4 DDR3 SDRAMs directly on the pcb). The lead-in section to me would start from the DDR3 controller address pin to the junction point of first SDRAM.

If I have to propose a routing guideline BEFORE DOING ANY SIMULATON, I believe this will be the ideal board routing guideline:

For the whole lead-in section (from CAC pins of DSP DDR3 controller section to first SDRAM junction), I should route with a wider board trace (i.e., low impedance, say 40 ohms). Then, for all the loaded sections (i.e., rest of the trace till VTT terminating resistor), I should route with a thinner board trace (i.e., high impedance, say 50 ohms).

My doubts are:

[a] In the above ideal routing recommendation, since this loaded section is upto terminating resistor of 39 ohms, won’t the signal see a 10 ohms impedance discontinuity (50 ohms to 39 ohms) at the end? This causes a portion of the signal to reflect back causing more signal degradation. How bad is the signal degradation caused by this reflection?  Can we ignore it?

[b] If the CAD team finds that it difficult to implement the above case, and that  we have to provide them with one trace impedance (either 50 ohms or 40 ohms); which one is better?

If I route 40 ohms throughout, I have an impedance discontinuity at the first SDRAM, but the signal terminates properly at the end without any reflection going back.

If a route 50 ohms throughout, the signal first sees an impedance discontinuity at the first SDRAM. Then, as the signal reaches the end, it sees a 10 ohms impedance discontinuity. This causes a portion of the signal to reflect back causing more signal degradation.

Thinking this way, 40 ohms looks better. What is your view?

[c] In the same document under the section - "Plane Referencing", it tells the DIMMs are using VDD plane as a reference for Address, Command, Control and VREFCA, and clocks.

[c.1] I believe they are talking about the routing that will be done in DIMM pcb and not inside the actual SDRAM chip. Am I correct?

[c.2] Under the section “Routing Rules – Address and Command Lines (UDIMMs)” of the the keystone DDR3 controller design guideline (SPRABI1C), it tells that it is best to route Address, Command, Control lines over a solid ground plane. I am planning to do just that. Route everything (data, clocks, and all CAC signals) over a solid ground plane. I think it shouldn't create a problem in my case because I am not using DIMM pcb. Do you think my approach is ok?

Thanks and Regards,

Binayak

Dear Bill,

Sorry for the delay. I was going through some literature regarding the same issue. My response is little long, so please bear with me.

I went through the document you had referred.

As per the TI appnote (SPRABI1C), KeyStone-I device will present a 45-Ω output impedance when driving CAC signals. I am using the VTT terminating resistor of 39 ohms.

First I modified the definition of lead-in section because I'm not using DIMMs (I am mounting 4 DDR3 SDRAMs directly on the pcb). The lead-in section to me would start from the DDR3 controller address pin to the junction point of first SDRAM.

If I have to propose a routing guideline BEFORE DOING ANY SIMULATON, I believe this will be the ideal board routing guideline:

For the whole lead-in section (from CAC pins of DSP DDR3 controller section to first SDRAM junction), I should route with a wider board trace (i.e., low impedance, say 40 ohms). Then, for all the loaded sections (i.e., rest of the trace till VTT terminating resistor), I should route with a thinner board trace (i.e., high impedance, say 50 ohms).

My doubts are:

[a] In the above ideal routing recommendation, since this loaded section is upto terminating resistor of 39 ohms, won’t the signal see a 10 ohms impedance discontinuity (50 ohms to 39 ohms) at the end? This causes a portion of the signal to reflect back causing more signal degradation. How bad is the signal degradation caused by this reflection?  Can we ignore it?

[b] If the CAD team finds that it difficult to implement the above case, and that  we have to provide them with one trace impedance (either 50 ohms or 40 ohms); which one is better?

If I route 40 ohms throughout, I have an impedance discontinuity at the first SDRAM, but the signal terminates properly at the end without any reflection going back.

If a route 50 ohms throughout, the signal first sees an impedance discontinuity at the first SDRAM. Then, as the signal reaches the end, it sees a 10 ohms impedance discontinuity. This causes a portion of the signal to reflect back causing more signal degradation.

Thinking this way, 40 ohms looks better. What is your view?

[c] In the same document under the section - "Plane Referencing", it tells the DIMMs are using VDD plane as a reference for Address, Command, Control and VREFCA, and clocks.

[c.1] I believe they are talking about the routing that will be done in DIMM pcb and not inside the actual SDRAM chip. Am I correct?

[c.2] Under the section “Routing Rules – Address and Command Lines (UDIMMs)” of the the keystone DDR3 controller design guideline (SPRABI1C), it tells that it is best to route Address, Command, Control lines over a solid ground plane. I am planning to do just that. Route everything (data, clocks, and all CAC signals) over a solid ground plane. I think it shouldn't create a problem in my case because I am not using DIMM pcb. Do you think my approach is ok?

Thanks and Regards,

Binayak

Dear Bill,

Thanks for clearing my doubts. I will probably go with 50 ohms throughout, now that I know the pros and cons of using 40 ohms vs 50 ohms.

Thanks and Regards,

Binayak