DRA829V: [DRA829]OSPI mode startup confirmation

Xie,

which SDK you use?

Regards,

Yordan

HI Yordan,

1,We use cypress nor flash, the chip model is s28hs512t, and the SDK version is psdk_ rtos_ auto_ J7_ 06_ 02_ 00_ 21. The address of SBL storage is 0x400000,

2.The boot mode is that OSPI has no backup mode and OSPI mode fails to start. The oscilloscope can be used to measure the CS, CLK and D [0], d [1] signals of flash, but UART does not print any information (UART channel is OK).

3,The primary mode of boot is OSPI, and the backup mode is UART boot mode. You can use an oscilloscope to measure the signals of CS, CLK and D [0], d [1] of flash, but it will automatically switch to UART boot mode, and UART will print C all the time.

Is the ROM code of dra829 not supporting nor flash of cypress? Or are there other problems?

Please reply as soon as possible,

regards,

Xie.

Hi Xie,

Xie Linda said:

We use cypress nor flash, the chip model is s28hs512t, and the SDK version is psdk_ rtos_ auto_ J7_ 06_ 02_ 00_ 21. The address of SBL storage is 0x400000

Can you please clarify where the 0x400000 address comes from?

I would believe that the ROM code will try to look for the SBL image at 0x0 offset of the flash.

Xie Linda said:

The primary mode of boot is OSPI, and the backup mode is UART boot mode. You can use an oscilloscope to measure the signals of CS, CLK and D [0], d [1] of flash, but it will automatically switch to UART boot mode, and UART will print C all the time.

This is because from your primary boot media, ROM could not pick up the bootloader and hence falls to the backup boot mode.

Regards,

Karan

HI Karan,

I found the ROM from 0x400000 address in another post, the link is as follows: https://e2e.ti.com/support/processors/f/791/t/884999?tisearch 

Hi Xie,

Can you please flash you SBL 0x0

sysfw.bin on 0x40000

and application at 0xA0000

Regards,

Karan

Hi Karan,

OK, I will try startup from 0x0 address.

And I also have another question, when I debug the sbl project the M3(DMSC) core verification failed, the code is below. what is the reason for verification failed??

Regaers,

Xie

Hi Xie,

The code snippet you attached, that is while boot from which boot media?

Regards,

Karan

Hi Karan,

The code snippet is uses OSPI boot mode, and  the pLocalRespHdr->type value is 0x8805U, but the pLocalRespHdr->flags value is 0xffffffU. So what went wrong?

Regards,

Xie,

Hi,Karan

I tried to use OSPI mode (MCU boot 00 0100 0000, Boot 0000 0000) to start from address 0x0, no LOG is printed out, so the ROM did not find the corresponding SBL file.

But I use SPI mode (MCU boot 00 0110 0000, Boot 0000 0000) to start from address 0x0, it is possible to find a valid SBL file, but the M3 core verification fails, how to solve this problem? At the same time, please try to use the SPI mode to start the M3 verification failure on your development board.

Please reply as soon as possible.

Regards,

Xie

Hi Xie,

Are you trying out an existing example or is it a custom example? Is it working from other boot mode?

Is it possible for you to send me your images - app, sysfw.bin and SBL? I want to test it on the EVM and make sure that it works here.

Regards,

Karan

Hi Xie,

Thanks for the update, this information will be useful for a lot of people trying out Cypress's norflash. Can you please list all the changes you made?

Regards,

Karan

Karan Saxena said:

谢你好

您是在尝试现有示例还是自定义示例？它可以在其他启动模式下工作吗？

您是否可以将我的图像（应用程序，sysfw.bin和SBL）发送给我？我想在EVM上对其进行测试，并确保它在这里可以正常工作。

问候，

卡兰

Hi,Karan

I'm sorry, I can't send these files to, because the company prohibits the transmission of these files. But I can tell you how I generated these files:
 I use sysfw.bin in SDK6.01, the sbl file is compiled from sbl_ospi_img in sdk6.01, and then the appimage file can use any one, such as dio_app.

Regaeds,

Xie