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AM3874: LCD data corruption

Part Number: AM3874

Hi,

My customer is using AM3847 and reported display image corruption.

Here is their usecase:
- RGB data are in DDR3
- RGB data are transferred from DDR3 to HDVPSS(VPDMA =>GRPX=>HD_VENC_D) to LCD output.
- Cortex-A8 writes new data in DDR3

Issue:
The LCD image sometimes corrupted as if it is divided horizontally.
The upper part and the lower part are from different images.
I think it is possible the image is corrupted if VPDMA and Cortex-A8 does not handshake properly.

Questions:
1) Is there any way Corte-A8 knows VPDMA transfer start/stop timing?
2) Do we have any sample configuration / code to avoid such issue (double buffer, ping-pong buffer, etc.)?

Thanks and regards,
Koichiro Tashiro

  • Koichiro, 

    can you check the hand-shaking between A8 and VPDMA - is there a cache write back function by A8, after it puts data into DDR3? you mentioned: 

       >> Cortex-A8 writes new data in DDR3

    if i assume these data are indeed CPU written, then either of the following shall happen:

    1. The display buffers are defined as non-cacheable to A8, or, 

    2. A8 need to flush cache once it is done to write. 

    Regards

    Jian

  • Thank you for your reply.

    I am Ando asking a question via Koichiro.

    I have confirmed that the display buffer is defined in a non-cache area.

    I only use one side of the display buffer.
    I guess the cause is as follows.
    ・The frame buffer write by A8 is not synchronized with vertical sync.

    I think that the following means are necessary to solve it.
    ・Synchronize the frame buffer write by A8 with vertical sync.
    or
    ・A8 writes to the display buffer that can be written by the ping-pong buffer.


    I have the following questions.
    ・How can the A8 detect vertical sync (or end of frame)?
    ・It is presumed that it is necessary to notify A8 of the DMA completion timing of VPDMA in order to use the ping-pong buffer.
     Is there any docs or sample code to help me with a ping pong buffer that covers the VPDAMA and A8 handshakes?

    Regards

    Ando

  • Ando, 

    Can you confirm if you are using the EZSDK or just bare-metal? There may be some IPC examples on how to sync up between ARM and VPDMA events. There may be some software framework such as OpenMax (may be an overkill) as mentioned in:

    https://software-dl.ti.com/dsps/dsps_public_sw/ezsdk/5_04_00_11/exports/DM814x_EZ_Software_Developers_Guide.pdf

    But if you need some low-touch by the A8 on the display data, no GPU, then just the IPC shall be fine, where you would like to:

    1. Build a set of buffer pool in DDR, then let A8 and the Media Controller share their handles. If A8 is not doing other tasks, and he can finish display processing at a fraction of the 33ms (assuming you are displaying 30fps), then a ping-pong buffer is sufficient. Otherwise, make a buffer pool 3-6 frames deep. Once system is reaches equilibrium, three buffers shall be active at any given time. 

    2. Management of buffer handles across the A8 and media controller can be based on IPC. I assume you use the media controller to manage VPDMA. 

    3. Buffers get recycled and only have one owner at any given time. 

    Not sure I understand your notes on:

    >>The frame buffer write by A8 is not synchronized with vertical sync.

    As the VSyn is generated by the DSS hardware, A8 can not really directly control the Vsync. The display engine will need to be fed by the VPDMA when its internal FIFO reaches lower bound. At the same time, it sends out Hsync/Vsyn according to display resolution and frame rate. 

    please let me know if I misunderstood you. sorry for the slow response. 

    Jian