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DRA77P: It is necessary a master Clock when McaASP configured slave and in SYNC mode?

AClemotte
Expert 1060 points
Part Number: DRA77P

Hi,

I have a question about the Jacinto McASP that I cannot resolve clearly. We currently have 3 devices connected to our Jacinto through 3 different McASPs. These 3 McASPs act as slaves in the I2S communication and are configured in SYNC mode. The McASP pins are configured as follows:

  • two data lines, one input and one output.
  • input bit clock
  • input frame clock
  • input master clock

The figure below tries to be an idea of our configuration:

My doubt is about the input master clock:

  1. it is really necessary in this case? As far as I understand, no, but I'm not sure.
  2. If not, could you tell us in which cases, being the McASP configured as slave, could the master clock be useful? For the only case I can think of is when the McASP is a teacher.
  3. if yes, Is the connection to the XREF OK? Since the AHCLKX is only output, I guess you have to use the XREF, right?

Regards,

  • 0
    TI__Genius 15120 points

    Hi AClemotte,

    1. McASP is a clock receiver in this case. XREF_CLK (note, this only one from many options) can be a clock source to McASP, when McASP provides the bit clock. Note also that McASP receive and transmit clocks can be configured and sourced independently, if required.

    3. A(H)CLKX can be also be sourced from internal SoC sources. XREF_CLK is an option if  Rx/Tx  must be synchronized to external device (video stream for ex.)  Note also XREF_CLK is not a dedicated pin to McASP, but rather a top-level,optional, clock input to SoC.

    If you didn't have a chance to look at the TRM McASP chapter, kindly start with 26.6.4 McASP Functional Description, Figure 26-119. McASP Module Block Diagram, Figure 26-120. Transmit Clock Generator Block Diagram. There are also several clock muxes related to McASP in Chapter 3, PRCM.

     As I said previously, McASP has a very flexible clock distribution, not very easy to explain in a forum post.

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Expert 1060 points

    Hi Stan,

    I'm going to reframe my question, I hope to explain myself better. If the McASP receives both the bit clock and the frame clock (as seen in the figure above), does it need to receive master clock in order to decode audio? My hypothesis is that no, can you confirm this hypothesis?

    Regards,

    Alejandro.

  • 0 in reply to AClemotte
    TI__Genius 15120 points

    Alejandro,

    McASP will transmit (and receive, if configured to sync mode) audio data on every bit clock received on the aclk pin.

    McASP will need a  clock source (Soc internal, or SoC external [XREF_CLK]) to generate  bit clock on the aclk pin when McASP is the clock master.

    I'm not aware whatfor is the master clock on your I2S devices. Kindly check in the devices' datasheet for usage suggestions.

    I also warmly recommend you to check Figure 26-119. McASP Module Block Diagram and Figure 26-120. Transmit Clock Generator Block Diagram for McASP clocking details.

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Expert 1060 points

    Hi Stan,

    Here my comments.

    [TI] McASP will transmit (and receive, if configured to sync mode) audio data on every bit clock received on the aclk pin.

    [ACM] McASP will be configured as slave sync mode, so, it'll receive bit clock.

    [TI] McASP will need a  clock source (Soc internal, or SoC external [XREF_CLK]) to generate  bit clock on the aclk pin when McASP is the clock master.

    [ACM] My question is about this topic. Since the McASP will be slave / sync it will not need to generate the bit clock, so the master clock will not be necessary, it is my assumption. I wanted confirmation regarding this assumption.

    [TI] I'm not aware whatfor is the master clock on your I2S devices. Kindly check in the devices' datasheet for usage suggestions.

    [ACM] Don't worry about the external device generating the master clock. My question is if the McASP in slave / sync mode needs the master clock as input.

    Regards,

  • 0 in reply to AClemotte
    Expert 1060 points

    Hi Stan,

    Do you have any comments about my last post?

    Regards,

  • 0 in reply to AClemotte
    TI__Genius 15120 points

    Hi Alejandro,

    If you still have doubts, please see also the following guide:

    Here is one of the relevant sections:

    Regards,

    Stan