AM3357: CPSW communication issue

Kanae,

From your description above, it seems the issue actually has been resolved, but the customer need more clarification to the questions they have. I will try to get the answers by Friday.

Regards,

Garrett

Hi Garrett,

Thank for your reply.

Yes, my customer needs to know more clarification to the questions,
because they have to explain their end customer.

Please answer above questions, including whether the customer's measures are correct, or not.

Best regards,
Kanae

Hi Garrett,

My customer has an additional question here.

Q4. What are the conditions for CPSW to stop?
   Specifically, does it depend only on "Disable" setting of the ALE port?
   Or is it related to other settings?
   If so, what are the settings?

I am waiting for your answer to the above Q4 in addition to the previous Q1-Q3.
Thank you for your support!

Best regards,
Kanae

Hi Kanae,

I have reached out to Schuyler who helped the referenced thread to look into the Q1 and Q4.

For Q2, if the customer can step into the code, it should be able to find out where to set CPDMA.TX_INTMASK_SET. I don't have a EVM to replicate the issue at this time.

For Q3, you probably meant the configuration of CPSW#1 and CPSW#2 are the same but only one of the ports is connected? There is actually no known issues with functions like CPSW_ALE.PORTCTL.

Regards,

Garrett

Hi Garrett,

Thank you for your support!

For Q2, I will ask my customer to step into the code.

For Q3, Yes. My customer sets to connect only Port1 (port0 and port1: enable).
What you mean is if only one of the ports is connected,
there is no known issues with functions like CPSW_ALE.PORTCTL.
Is my understanding correct?
When the same setting of both CPSW # 1 and CPSW # 2 like CPSW_ALE.PORTCTL in this time,
is there any known issues with other functions?

I am waiting the answers for Q1 and Q4.

Best regards,
Kanae

Hi Garrett,

Could you please inform the date you will have the answers for Q1 and Q4 from Schuyler?

I would appreciate your continued support.

Best regards,
Kanae

Hi Garrett,

For Q2, my customer replies.

Q2-1.
Regarding Q2,
CPDMA.TX_INTMASK_SET is set by EMAC_cpdmaDMAIntEnable() called from EMAC_cpdmaOpen().
The intention of Q2 is that CPDMA.TX_INTMASK_SET register simply looks like an interrupt mask register
for each TX0 to TX7 in AM335x:TRM

However, in the source code, it is set with the define macro value described in Q2,
and the function imagined from the define macro value and the description of TRM are inconsistent.
Which is correct, TRM or the source code?

Here is his additional question.
Q5. Is there a recommended design flow when deciding the register setting value of CPSW_ALE?

I am waiting the answers for Q1 Q2-1, Q4 and Q5.

Best regards,
Kanae

Hi Kanae,

For Q1:

A condition might be that the FIFO is full, e.g. unused port is enabled, multicast/broadcast packets will be forwarded to unused port and, after sometime, finally just fill fifos full, after that cpsw will just push back all new TX requests (or even can stack).

For Q2-1:

Please refer to 14.3.1.3.4.2 Statistics Interrupt and 14.3.1.3.4.3 Host Error Interrupt, both interrupts can be read by reading the TX_INTSTAT_RAW and TXINTSTAT_MASKED registers, respectively.

For Q4:

Unused port:

- ALE port must be disabled

- MAC SL must be disabled

- Control module gmii_sel register for this port must be in default state

For Q5: 

Please refer to 14.4.6 Initialization and Configuration of CPSW, 14.3.2.7 Address Lookup Engine (ALE) and the CPSW driver example such as EMAC_AleInitLoopback()

Regards,

Garrett

Hi Garrett,

Thank you for your reply!

Also, please continue to support us
as my customers ask additional questions.

Best regards,
Kanae

Hi Garrett,

My customer has asked additional questions about your reply.

For Q1.
Are you sure that there is no condition for CPSW to stop except when the FIFO is full?
Please let us know if there are other possible conditions.

For Q2-1.
The value of the CPDMA.TX_INTMASK_SET register is 2.
However, transmission uses only TX0, so 1 should be sufficient.
Please reply again whether TRM or source code is correct.

For Q4:
The status under the transmission does not start are "AND" of
the following 3 conditions you replied.
Is this understanding correct?

Unused port:
- ALE port must be disabled
- MAC SL must be disabled
- Control module gmii_sel register for this port must be in default state

I appreciate your continued support.

Best regards,
Kanae

Hi Garrett,

Please just let me know when you can reply the above questions.

Best regards,
Kanae

Hi Kanae,

I was out of town, will look into the questions today and reply...

Regards,

Garrett

Kanae,

For Q1: We are not aware of other possible conditions except the ones listed in 14.3.1.3.4.3 Host error Interrupt and the FIFO full.

For Q2: The TRM should be correct. Let me clarify with the driver developer to see why HOST_ERR_INT_MASK is set to CPDMA.TX_INTMASK_SET bit 1.

For Q4: To ensure transmission start, the 3 conditions need to be 'AND'.

Regards,

Garrett

Hi Garrett,

Thank you for your support!

Please check with the driver developer about Q2.
If it's going to take a long time, just let me know when you can get a response.

Best regards,
Kanae

Hi Garrett,

Do you have a schedule to check with the driver developer about Q2?
I need to inform my customer, please just let me know your plan.

I appreciate to your help.

Best regards,
Kanae

Hi Kanae,

I confirmed with the developer that CPDMA.TX_INTMASK_SET should only have bit 0 set for TX Channel 0 transmit completion interrupt EMAC_cpswHwIntTx().

There is no host error nor statistics interrupt routine in the driver, and even if it's supported, the bits should be set in DMA_INTMASK_SET Register (offset = B8h) instead of TX_INTMASK_SET Register (offset = 88h).

Please let us know if you see any issue with only bit 0 set in TX_INTMASK_SET register.

Regards,

Garrett

Hi Garrett,

I would like to make sure about your answers of Q2 and Q4.

====================================================
For Q2 dated Jun-23:
I confirmed with the developer that CPDMA.TX_INTMASK_SET should only have
bit 0 set for TX Channel 0 transmit completion interrupt EMAC_cpswHwIntTx().
There is no host error nor statistics interrupt routine in the driver,
and even if it's supported, the bits should be set in DMA_INTMASK_SET Register
(offset = B8h) instead of TX_INTMASK_SET Register (offset = 88h).
Please let us know if you see any issue with only bit 0 set in TX_INTMASK_SET register.
====================================================

Q2-1.
When using TX channel 0-only transmission completion interrupts,
only bit 0 should be set, so TX_INTMASK_SET Register should set it to "1"
in order to avoid unnecessary settings. Is that correct?

====================================================
For Q4:
Unused port:
- ALE port must be disabled
- MAC SL must be disabled
- Control module gmii_sel register for this port must be in default state
====================================================

Q4-1.
Does "MAC_SL" refer to "CPSW_SL1.MACCONTROL" and "CPSW_SL2. MACCONTROL"?
If they make to be disabled, should they be set with the hardware default value of 0?

Best regards,
Kanae

Kanae,

>>Q2-1.
>>When using TX channel 0-only transmission completion interrupts, 
>>only bit 0 should be set, so TX_INTMASK_SET Register should set it to "1" 
>>in order to avoid unnecessary settings. Is that correct?

Yes, that's correct.

>>Q4-1.
>>Does "MAC_SL" refer to "CPSW_SL1.MACCONTROL" and "CPSW_SL2. MACCONTROL"?
>>if they make to be disabled, should they be set with the hardware default value of 0?

Bit 5 GMII_EN setting to 0 should be sufficient but using the hardware default value of 0 is OK too.

Regards,

Garrett

Hi Garrett,

Thank you for your support!

Best regards,
Kanae