AM4379: FIFO behavior in ADC example

Hi Thomas,

Sorry for taking so long to respond.

>> I assume that every access to the FIFO register forces the sequencer internally to provide data content of next enabled step.

The FSM executes enabled steps in sequence after a SW or HW trigger. Enabled steps are executed, and ADC output samples are written to the FIFO selected for the each step.

>> But when accessing FIFO data first to get 12 bit data and then to extract 4 bit step ID tag using TI's functions, 2 consecutive register accesses are done. Is the result (data couple of value and step ID tag) consistent? For that case I would expect expect that it's necessary to read complete 32 bit and mask afterwards.

The Startware ADC example <PDK>\packages\ti\starterware\examples\adc (and Suresh's modified
example) calls the function TSCADCFIFOADCDataRead() to obtain sampled data from FIFO0 and FIFO1 once the main thread detects the End Of Sequence interrupt has occurred. This function performed a 32-bit read of the selected FIFO.

uint32_t TSCADCGetFifoData(uint32_t baseAddr, uint32_t fifoSel)
{
    uint32_t fifoReg = 0;

    if (TSCADC_FIFO_SEL_0 == fifoSel)
    {
        fifoReg = ADC0_FIFO0DATA;
	}
    else
    {
        fifoReg = ADC0_FIFO1DATA;
    }

    return(HW_RD_FIELD32((baseAddr + fifoReg), ADC0_FIFO0DATA_ADCDATA));
}

I agree two reads of the FIFO will return two different results, and the sampled data and sequence ID won't match for the two separate reads.

>> I haven't found a description how it is managed to provide different channel data by only reading identical register all the time.

Enabled steps write the selected channel output the selected FIFO (0 or 1). This is described in the TRM, 11.4 Operational Modes. A FIFO output is accessible from a single memory-mapped location. 

>> I was wondering if there could be inconsistent data 'couples' if first 12 bit data value is read and 4 bit step ID tag afterwards (2 register accesses using TI functions).

Yes, the data would be inconsistent for two different reads. Which TI functions are referring to?

>> And I asked myself why there is a size of 64 entries with 16 bit for each FiFo.
>> Is this size required for sampling by average?

Each 16-bit entry contains a 4-bit step tag along with a 12-bit ADC sample.

64 entries provides buffering for ADC samples to avoid overrun, i.e. the time constraint for the CPU or DMA reading the samples is relaxed.

Averaging is performed before the data is written to the FIFO, please see this comment in the TRM, 11.3.3 Averaging of Samples (1, 2, 4, 8, and 16):

If averaging is turned on, then the channel is immediately sampled again (up to 16 times) and final averaged sample data is stored in the FIFO.

Regards,
Frank