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CCS/SM320C6727B-EP: Design flow for the C6000 ROM bootloader

Prodigy 20 points

Replies: 2

Views: 42

Part Number: SM320C6727B-EP

Tool/software: Code Composer Studio

Hi All,

I am working with custom hardware using a C6727 DSP. The memory is split between SDRAM and parallel NOR flash memory with the goal of storing the application in flash and running it out of the external RAM. The internal ROM bootloader will be required, for which I've gathered testing uses the following procedure:

1. Write the application (for starters, a simple Hello World)  

2. Combine this with the provided secondary bootloader in sprc203 and create an output file in CCS

3. Create a config file using the genAIScfg tool (I believe an older version of Perl is required which is now behind a paywall) This will need to be manually crafted to initialize the PLL/Flash/SDRAM properly. Since I don't want to pay for the legacy version I'll only have reference cfg files from the PADK. 

4. Integrate the cfg file and the .out file for the application using the genAIS tool into a single .ais file.

5. Write a separate application that initializes the PLL/Flash/UHPI extended address GPIOs and then writes the .ais file into flash memory.

6. Switch to flash bootmode and the bootloaders should take care of starting the program. 

There is quite a lot of work involved to simply test the bootloader. I've reviewed spraa69d, the chip support library api, and the individual interface documents for EMIF/UHPI/PLL, but before I start tackling each of these components, I wanted to know if there are any other resources or pre-built applications I'm missing that could simplify this procedure. For example:


- Is there a workaround for the genAIScfg app not working with the latest version of Perl?

- Besides the PADK files, are there examples of the secondary bootloader being used in a similar use case, or linker files that set up the flash/sdram environments correctly?

- I originally wrote a GEL script to initialize the SDRAM, and I will need to do this same process again in the cfg and using the csl just to get each of these components working. Is there a way to reduce any of this redundancy?

I am new to most of this, so any advice on this matter would be useful (even if it's to say that I already have all the tools I need here or that I'm dumb and there's a button to do all of this in Code Composer)


Thanks,
Trent

  • Trenten,

    This is a fairly old device where there is very low boot expertise left within TI. I would recommend that you use the following bootloader application notes as reference to set this up at your end:

    https://www.ti.com/lit/an/spraa69d/spraa69d.pdf

    You may also want to refer the tutorial archived here:

    https://www.daycounter.com/LabBook/TMS320/C6722_Tutorial.phtml

    If you are planning to use parallel flash then at the E2E discussion here for guidance on use of secondary bootloader:

    https://e2e.ti.com/support/processors/f/791/p/12367/48343

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  • In reply to Rahul Prabhu:

    I figured as much. Thanks for taking the time to reply! The information you provided at the very least proves out my procedure.

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