AM5746： GPMC_CLK

Kanae

Part Number: AM5746

Hi Sitara support Team,

According to Figure 15-70, GPMC_CLK stops when CYCLE time completes.

My customer would like to confirm this as it affects the design of the receiver side FPGA.

Is it possible to set GPMC_CLK not to stop?

Best regards,
Kanae

over 3 years ago

0 Kanae over 3 years ago

Mastermind 9635 points

Hi Sitara Support Team,

I refer the this thread, but it did not solve the last question.

*****

is it not possible to use gpio6_16.clkout as GPMC_CLK in the following cases?

GPMC_FCLK = 266 MHz
GPMCFCLKDIVIDER = 0x2: GPMC_CLK frequency = GPMC_FCLK frequency / 3
GPMC_CLK = 88 MHz

******

I would like to know the answer, if it is not possible to set GPMC_CLK to keep running.

Best Regards,
Kanae

0 Shiou Mei Huang over 3 years ago in reply to Kanae

TI__Genius 10180 points

Kanae,

GPMC_CLK cannot be free running. Customer can use GPIO6_6.CLKOUT1 as an "always-on" alternative, but note this clk cannot be used to replace GPMC_CLK to latch data from the bus.

More details can be found in this post here: https://e2e.ti.com/support/processors/f/791/p/674641/2490132?tisearch=e2e-sitesearch&keymatch=gpio6_16%2520programmed#2490132

Have a great day!

Best Regards,

Shiou Mei

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AM5746： GPMC_CLK