Hi
The customer wants to test and evaluate ECC function.
In the Application Report of “AM65x DDR ECC Initialization and Testing(SPRACM1-September 2019)”, Chapter 9 “Testing ECC” mentions about “DDR stress tests” like below;.
• DDR stress tests can be utilized to validate the configuration of the DDR memory (including ECC byte
lane), to prove that the DDR timings have margin, and that the layout is not impacted by crosstalk,
signal integrity issues, and so forth.
Do you have this stress tests tools or sample code ?
If you have it, could you share it with us ?
Thanks and regards,
Hideaki