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66AK2G12: Connecting 18 bit ADC sampling at 40ksps over SPI and DMA to 66AK2G12 processor

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Part Number: 66AK2G12

  • We are planning to connect LTC 2344-18 ( ADC to the 66Ak2G12 Processor. LTC 2344-18 ADC is 4 channel 18 bit ADC. It transfers 24 bits/channel, 18 bit of digital data, 3 bits of channel ID, 3 bits for SPAN.
  •  Sampling rate is 40KSPS.
  •  LTC 2344-18 requires CNV signal to begin the ADC conversion process.So the CNV signal has to be activated every 25 micro-seconds.

My queries are as below:
1. When does SPI clock gets generated
a. Is it when CS make high to low transition and after a delay of C2TDELAY? OR
b. Is it when data is written to SPIDAT1 register

2. How can we receive 24 bits of data into SPI buffer as the maximum character length in SPI in 16 bits

3. Since we are having high sampling rate my plan was to use the DMA to receive the data from ADC and transfer it to the RAM location
But the Conversion start signal to ADC has to be provided which I was thinking of providing by enabling the SPIm_CS signal(connected to CONV pin of ADC) for required pulse width(tconv =40ns))in interrupt handler and disabling it. Is there a way we can automate it, since the whole purpose of DMA (no interruption to processor) is getting nullified with this approach.

  • Sudhendra Nayak
    1. When does SPI clock gets generated
    a. Is it when CS make high to low transition and after a delay of C2TDELAY? OR
    b. Is it when data is written to SPIDAT1 register

    Please refer to the TRM chapter for SPI Operation in 4 pin mode. The clock gets generated when CS make high to low transition and after a delay of C2TDELAY

    Sudhendra Nayak
    How can we receive 24 bits of data into SPI buffer as the maximum character length in SPI in 16 bits

    This can be managed at the SPI driver level where you can have 24 bits sent as a burst from the LTC2344 and the SPI is configured to receive 3 messages of 8its characters. After they are received they can be packed as required.

    Sudhendra Nayak
    3. Since we are having high sampling rate my plan was to use the DMA to receive the data from ADC and transfer it to the RAM location
    But the Conversion start signal to ADC has to be provided which I was thinking of providing by enabling the SPIm_CS signal(connected to CONV pin of ADC) for required pulse width(tconv =40ns))in interrupt handler and disabling it. Is there a way we can automate it, since the whole purpose of DMA (no interruption to processor) is getting nullified with this approach

    You can potentially explore the use of PRU ICSS subsystem and its GPIOs for the additional signalling.

    Regards,

    Rahul

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