AM4378: ARM to PRU event

R2d2

Hi Team,

I am trying to configure the PRU to identify the PWM3 interrupt event

Arm is configure to generate an interrupt @ PWM3 timer Period (see below sample code, that assume timer setup has already been performed) and when debugging I see that interrupt MyISR is indeed executed.

I than setup ICSS0 , PRU 0 and enable event 43

CT_INTC.ESR1 = 0x00000800 (bit 11) and monitor CT_INTC.SECR1 . I'd expect to see bit 11 of SECR1 set, but it doesn't

can you help me figure out what is missing ?

ARM setup :

setup epwm counters and than :

1) configure the event

CSL_epwmEtIntrCfg(SOC_PWMSS3_REG, CSL_EPWM_ET_INTR_EVT_CNT_EQ_ZRO,
CSL_EPWM_ET_INTR_PERIOD_FIRST_EVT);

2) configure the Hwi

Hwi_Params_init(&hwi_params);
hwi_params.priority = 2;
hwi_params.enableInt = 1;
Error_init(&eb);
Hwi_create(epwm_intr, MyISR, &hwi_params, &eb); // epwm_intr == 173

over 3 years ago

0 Garrett Ding over 3 years ago

TI__Mastermind 43296 points

Hi,

This is not specific to pwm, but please check if this PRU interrupt configuration help:

https://git.ti.com/cgit/pru-software-support-package/pru-software-support-package/tree/examples/am437x/PRU_PRUtoARM_Interrupt

Regards,

Garrett

0 R2d2 over 3 years ago in reply to Garrett Ding

Expert 1130 points

Hi Garrett,

I tried to do the same as the example (See below) , but i still see no interrupts ,a or pending interrupts

(note that the demo code is pru to arm interrupt , while I am working on arm to pru interrupt)

can you please help ? I do not see the appropriate SECR1 bit change or any changes to R31

do I need to set appropriate bit @ PRU_ICSS_INTC_ERS1 ? ( in the below demo CT_INTC.ESR1 |= PRU0_ARM_EPWM3_EVENT_MASK) ? I tired this , but it did not seem the have any affect

#define HOST_NUM 1
#define CHAN_NUM 1
#define PRU0_ARM_EPWM3_EVENT 43
#define PRU0_ARM_EPWM3_EVENT_MASK (1 << (PRU0_ARM_EPWM3_EVENT - 32))

void main()
{

CT_INTC.GER = 0x1; // Globally enable host interrupts

__R31 = 0x00000000; // Clear any pending PRU-generated events
CT_INTC.HIEISR |= HOST_NUM; //Enable Host interrupt 1
CT_INTC.HMR0_bit.HINT_MAP_1 = HOST_NUM; // Map channel 1 to host 1
CT_INTC.CMR10_bit.CH_MAP_43 = CHAN_NUM; // Map epwm3 intr event to channel 1
CT_INTC.SICR = PRU0_ARM_EPWM3_EVENT; // Ensure PRU0_ARM_EPWM3_EVENT is cleared
CT_INTC.EISR = PRU0_ARM_EPWM3_EVENT; // Enable PRU0_ARM_EPWM3_EVENT

/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */

CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;

/* bring GPO low initially */
__R30 = 0x0;

while(1)

{

if ((CT_INTC.SECR1 & PRU0_ARM_EPWM3_EVENT_MASK) != 0)
{

++PRU0Interface.epwm3_event_counter; // for debug

CT_INTC.SECR1 = PRU0_ARM_EPWM3_EVENT_MASK; // clear the event

}

/* Disable UART before halting */
//CT_UART.PWREMU_MGMT = 0x0;

/* Halt PRU core */
//__halt();
}

0 R2d2 over 3 years ago in reply to R2d2

Expert 1130 points

Any leads on this one ?

0 R2d2 over 3 years ago in reply to R2d2

Expert 1130 points

anything on this one ?

0 Frank Livingston over 3 years ago in reply to R2d2

TI__Mastermind 28788 points

Hi,

I'm taking a look at the example code. I expect what's required it to configure the ICSS INTC to route ARM interrupts to Host INT0 or INT1 interrupts, which can be polled on the PRU cores.

Regards,
Frank

0 R2d2 over 3 years ago in reply to Frank Livingston

Expert 1130 points

Thanks Frank,

looking forward to hear from you

0 Frank Livingston over 3 years ago in reply to R2d2

TI__Mastermind 28788 points

How about this? This example is for ARM to PRU interrupt and contained in the same package shared by Garrett.

Regards,
Frank

0 R2d2 over 3 years ago in reply to Frank Livingston

Expert 1130 points

I saw this example

while it is labeled as ARM to PRU interrupt it does not include any interrupt setup expect an unused define. it does not seems relevant

0 R2d2 over 3 years ago in reply to R2d2

Expert 1130 points

Hi Frank

can you look into this ?

0 Frank Livingston over 3 years ago in reply to R2d2

TI__Mastermind 28788 points

Hi,

Yes, I'll take a closer look. This example should work for ARM to PRU interrupt.

Regards,
Frank

0 Frank Livingston over 3 years ago in reply to Frank Livingston

TI__Mastermind 28788 points

Hi,

My understanding is you want to route EPWM3INT to ICSSG0, PRU0. I think the only thing you're missing is the ICSSG0 INTC configuration.

Please see these sections in the AM437x TRM (spruhl7i.pdf):

30.4.2 Interrupt Controller (INTC).
30.4.2.5 INTC Basic Programming Model.

INTC can be configured from the PRU or ARM.

The PRU software package provides an example of configuring INTC from the PRU. Please see: https://git.ti.com/cgit/pru-software-support-package/pru-software-support-package/tree/labs/Hands_on_Labs/lab_4/solution/button_led_0

PRSDK provides the PRUSS Low-Level Driver (LLD) for the ICSSG which used on ARM, please see:

https://software-dl.ti.com/processor-sdk-rtos/esd/docs/06_03_00_106/AM335X/rtos/index_device_drv.html#pruss
<PDK>\packages\ti\drv\pruss
<PDK>\packages\ti\drv\pruss\docs

The PRUSS LLD API function for configuring INTC is PRUICSS_pruIntcInit(). Various drivers & examples in PRSDK use this function for configuring INTC. For example, please see:

<PDK>/packages/ti/drv/i2c/src/v2/I2C_v2.c:696: PRUICSS_pruIntcInit(pruIcssHandle, &pruss_intc_initdata);
<PDK>/packages/ti/drv/uart/src/v2/UART_v2.c:1656: retVal = PRUICSS_pruIntcInit(pruIcssHandle, &pruicssIntcInitdata);

Regards,
Frank

0 R2d2 over 3 years ago in reply to Frank Livingston

Expert 1130 points

many thanks for that

I'll work on it per your recomendation

0 R2d2 over 3 years ago in reply to R2d2

Expert 1130 points

Hi Frank,

can you take a look at this

https://e2e.ti.com/support/processors/f/791/t/503488?Cannot-acquire-an-interrupt-from-PWM-or-ADC-in-PRUICSS-INTC

it can explain what I see as I worte above : "CT_INTC.ESR1 = 0x00000800 (bit 11) and monitor CT_INTC.SECR1 . I'd expect to see bit 11 of SECR1 set, but it doesn't"

while I can find it in the documentation (though difficult to understand it is related ) , it does not appear on the pru_cfg.h file

in fact , this address is labeled reserved at the pru_cfg.h file I have

does it exists ? should I play with it ?

0 R2d2 over 3 years ago in reply to Frank Livingston

Expert 1130 points

I believe I am doing what is described in the documentation and the demo , but it still does not work.

I found an old thread that may be related but some clarifications are needed.

another option is a working demo (that I currently don't have) that will allow me to make sure I indeed doing all that is needed

0 R2d2 over 3 years ago in reply to R2d2

Expert 1130 points

Hi Frank

I changed the h file to include this register and it seems to resolve the problem

can you confirm its a documentation bug and that access to address offset 0x2c is indeed valid?

0 R2d2 over 3 years ago in reply to R2d2

Expert 1130 points

Hi,

anything about this ?

also - what is the proper way to clear the event

0 Frank Livingston over 3 years ago in reply to R2d2

TI__Mastermind 28788 points

Hi,

It seems the information in the thread you located is correct, but I can't say with complete certainty because the descriptions in the TRM are a bit confusing. I've looped in a colleague in case she knows more about this than I do.

The AM335x TRM, Table 30-30. PRU-ICSS0 System Events shows Event Number 43 is associated with epwm_intr_intr_pend in Standard Mode, and (pr1_mii0_col and pr1_mii0_txen) (external) in MII_RT mode. These footnotes are included with the table:

(1) MII_RT mode is selected through the MII_RT register in the PRU-ICSS0 CFG register space.
(2) Signals 63-56 and 31-0 for MII_RT Mode are the same as for Standard Mode.

The MII_RT register is described in Figure 30-304. PRU_ICSS_CFG_MII_RT Register. It can be seen here the default is 1h (R/W) = Enabled (use MII_RT events), while 0h (R/W) = Disabled (use the external events).

Events can be cleared by writing to either PRU_ICSS_INTC_EICR or PRU_ICSS_INTC_SECR0/1.

Regards,
Frank

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AM4378: ARM to PRU event