This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3352: Problem using two NAND flash

Part Number: AM3352

Hello,

We are using am3352 in our design with kernel 4.14.67 and U-Boot version 2019.01 from TI SDK.

We have been working with 1GByte nand flash, but now we need bigger memories, so we have included in our design a 4GByte nand flash (it has two different CS, one for each 2GByte).

Configuring the first 2GByte is working fine, but no way with the second CS:

- First we changed GPMC_MEM_END in omap-gpmc.c from 0x3FFFFFFF to 0xFFFFFFFF

- We changed device-tree file as follow:

    nandflash_pins_default: nandflash_pins_default {
        pinctrl-single,pins     = <
            0x00 (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0.gpmc_ad0           */
            0x04 (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1.gpmc_ad1           */
            0x08 (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2.gpmc_ad2           */
            0x0c (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3.gpmc_ad3           */
            0x10 (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4.gpmc_ad4           */
            0x14 (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5.gpmc_ad5           */
            0x18 (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6.gpmc_ad6           */
            0x1c (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7.gpmc_ad7           */
            0x70 (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0.gpmc_wait0       */
            0x8c (PIN_INPUT  | MUX_MODE2) /* (V12) gpmc_clk.gpmc_wait1   */
            0x7c (PIN_OUTPUT        | MUX_MODE0) /* gpmc_csn0.gpmc_csn0         */
            0x78 (PIN_OUTPUT        | MUX_MODE2) /* (U18) gpmc_be1n.gpmc_csn6         */
            0x90 (PIN_OUTPUT        | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
            0x94 (PIN_OUTPUT        | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren   */
            0x98 (PIN_OUTPUT        | MUX_MODE0) /* gpmc_wen.gpmc_wen           */
            0x9c (PIN_OUTPUT        | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
        >;
    }; /* nandflash_pins_default */

&gpmc {
    status                          = "okay";
    pinctrl-names                   = "default";
    pinctrl-0                       = <&nandflash_pins_default>;
    ranges                          = <0 0 0x08000000 0x80000000>,  /* CS0, NAND, 2GB max */
                                      <6 0 0x88000000 0x80000000>;  /* CS6, NAND, 2GB max */
    nand@0,0 {
        compatible = "ti,omap2-nand";
        reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
        interrupt-parent = <&gpmc>;
        interrupts = <0 IRQ_TYPE_NONE>,  /* fifoevent */
                 <1 IRQ_TYPE_NONE>;     /* termcount */
        rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
        ti,nand-ecc-opt             = "bch8";
        ti,elm-id                   = <&elm>;
        nand-bus-width              = <8>;
        gpmc,device-width           = <1>;
        gpmc,sync-clk-ps            = <0>;
        gpmc,cs-on-ns               = <0>;
        gpmc,cs-rd-off-ns           = <44>;
        gpmc,cs-wr-off-ns           = <44>;
        gpmc,adv-on-ns              = <6>;
        gpmc,adv-rd-off-ns          = <34>;
        gpmc,adv-wr-off-ns          = <44>;
        gpmc,we-on-ns               = <0>;
        gpmc,we-off-ns              = <40>;
        gpmc,oe-on-ns               = <0>;
        gpmc,oe-off-ns              = <54>;
        gpmc,access-ns              = <64>;
        gpmc,rd-cycle-ns            = <82>;
        gpmc,wr-cycle-ns            = <82>;
        gpmc,wait-on-read           = "true";
        gpmc,wait-on-write          = "true";
        gpmc,bus-turnaround-ns      = <0>;
        gpmc,cycle2cycle-delay-ns   = <0>;
        gpmc,clk-activation-ns      = <0>;
        gpmc,wait-monitoring-ns     = <0>;
        gpmc,wr-access-ns           = <40>;
        gpmc,wr-data-mux-bus-ns     = <0>;
        #address-cells              = <1>;
        #size-cells                 = <1>;

        /* MTD partition table */
        /* All SPL-* partitions are sized to minimal length
         * which can be independently programmable. For
         * NAND flash this is equal to size of erase-block
         */
        partition@0 {
            label                   = "NAND.SPL";
            reg                     = <0x00000000 0x00080000>;
        };
        partition@1 {
            label                   = "NAND.SPL.backup1";
            reg                     = <0x00080000 0x00080000>;
        };
        partition@2 {
            label                   = "NAND.SPL.backup2";
            reg                     = <0x00100000 0x00080000>;
        };
        partition@3 {
            label                   = "NAND.SPL.backup3";
            reg                     = <0x00180000 0x00080000>;
        };
        partition@4 {
            label                   = "NAND.u-boot-spl-os";
            reg                     = <0x00200000 0x00080000>;
        };
        partition@5 {
            label                   = "NAND.u-boot";
            reg                     = <0x00280000 0x00100000>;
        };
        partition@6 {
            label                   = "NAND.u-boot-env";
            reg                     = <0x00380000 0x00080000>;
        };
        partition@7 {
            label                   = "NAND.u-boot-env.backup1";
            reg                     = <0x00400000 0x00080000>;
        };
        partition@8 {
            label                   = "NAND.kernel";
            reg                     = <0x00480000 0x01000000>;
        };
        partition@9 {
            label                   = "NAND.file-system.backup1";
            reg                     = <0x01480000 0x04000000>;
        };
        partition@10 {
            label                   = "NAND.file-system";
            reg                     = <0x05480000 0x00>;
        };
    }; /* NAND@0,0 */
    
    nand@1,0 {
        compatible = "ti,omap2-nand";
        reg = <6 0 4>; /* CS6, offset 0, IO size 4 */
        interrupt-parent = <&gpmc>;
        interrupts = <0 IRQ_TYPE_NONE>,  /* fifoevent */
                 <1 IRQ_TYPE_NONE>;     /* termcount */
        rb-gpios = <&gpmc 1 GPIO_ACTIVE_HIGH>; /* gpmc_wait1 */
        ti,nand-ecc-opt             = "bch8";
        ti,elm-id                   = <&elm>;
        nand-bus-width              = <8>;
        gpmc,device-width           = <1>;
        gpmc,sync-clk-ps            = <0>;
        gpmc,cs-on-ns               = <0>;
        gpmc,cs-rd-off-ns           = <44>;
        gpmc,cs-wr-off-ns           = <44>;
        gpmc,adv-on-ns              = <6>;
        gpmc,adv-rd-off-ns          = <34>;
        gpmc,adv-wr-off-ns          = <44>;
        gpmc,we-on-ns               = <0>;
        gpmc,we-off-ns              = <40>;
        gpmc,oe-on-ns               = <0>;
        gpmc,oe-off-ns              = <54>;
        gpmc,access-ns              = <64>;
        gpmc,rd-cycle-ns            = <82>;
        gpmc,wr-cycle-ns            = <82>;
        gpmc,wait-on-read           = "true";
        gpmc,wait-on-write          = "true";
        gpmc,bus-turnaround-ns      = <0>;
        gpmc,cycle2cycle-delay-ns   = <0>;
        gpmc,clk-activation-ns      = <0>;
        gpmc,wait-monitoring-ns     = <0>;
        gpmc,wr-access-ns           = <40>;
        gpmc,wr-data-mux-bus-ns     = <0>;
        #address-cells              = <1>;
        #size-cells                 = <1>;

        /* MTD partition table */
        partition@11 {
            label                   = "NAND.data-storage";
            reg                     = <0x0000000 0x00>;
        };
    }; /* NAND@1,0 */
    

}; /* gpmc */

But when starting kernel I get this error

omap2-nand 88000000.nand: can't request region for resource [mem 0x88000000-0x88000003]

and after this a segmentation fault and a restart.

Could you please help us with this issue?

Best regards

Angel

  • Hi Angel,

    Please allow for a couple of days to look into this a bit closer (we have a holiday weekend coming up here too). Will get back on this early next week.

    Regards, Andreas

  • Angel,

    what P/N are you using? How is it connected? Not sure how you can interface with 4GBytes of NAND?? The AM335x SoC itself has only 32-bit address space, with only a portion of it that can be mapped via GPMC. From the TRM....

    "Support 512M Bytes maximum addressing capability which can be divided into seven independent chip-select with programmable bank size and base address on 16M Bytes, 32M Bytes, 64M Bytes, or 128M Bytes boundary"

    Also you cannot just change GPMC_MEM_END in omap-gpmc.c hoping to magically be able to address more memory. Everything that is configurable is done via DT, not by modifying driver files.

    Regards, Andreas

  • Hello Andreas,

    Thank you for your answer.
    First, I would like to say that you are right regarding changing drivers and configuration via DT. I was making changes on drivers just to help me to understand what was happening.

    Up to now we had been working with 1GByte and 2GByte NAND flash, so it is not a limitation 512Mbyte assigned to GPMC driver. Looking into TRM and these two links it is clear that it is possible to work with bigger NAND flash. NAND memory is a block device and it's not directly addressed by the GPMC address pins.

    e2e.ti.com/.../370130
    e2e.ti.com/.../388328

    My problem was that I did not know how to configure it in our DT, but now I found the solution. Both ranges must be within the 512Mbyte of GPMC driver

    ranges = <0 0 0x08000000 0x80000000>,  /* CS0, NAND, 2GB max */
             <6 0 0x10000000 0x80000000>;  /* CS6, NAND, 2GB max */

    Thanks for your help
    Angel

  • Angel,

    Angel Falcon said:
    My problem was that I did not know how to configure it in our DT, but now I found the solution. Both ranges must be within the 512Mbyte of GPMC driver

    ranges = <0 0 0x08000000 0x80000000>,  /* CS0, NAND, 2GB max */
             <6 0 0x10000000 0x80000000>;  /* CS6, NAND, 2GB max */

    thanks for clarifying the situation, and posting your solution back here. Glad to hear you got it working by only modifying the DTS.

    Regards, Andreas