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AM5746: Use QSPI SRAM with the AM5746 processor.

Part Number: AM5746

Hi Team,

I would like to use the QSPI SRAM with the AM5746 processor.
I'm going to make a new network system with the AM5746 processor. Also, I would like to use the QSPI SRAM with this system.
So, does this porcessor can connect such SRAM?
If yes, is there any materials about this?

Beat Regards,
Tom Liu

  • Hi Tom Liu,

    We do not have any materials on QSPI SRAM with AM57. Can you tell the exact part number
    So we can check if it is compatible.

    - Keerthy

  • Hi Keerthy,

    Does the part number mean AM5746 or SRAM?
    If you mean AM5746, there are 3 part number AM5746ABZX, AM5746ABZXA and AM5746ABZXEA,
    so could you check all of them?

    Beat Regards,
    Tom Liu

  • Hi,

    I want to know the part number of QSPI SRAM that you want to use.

    - Keerthy

  • Hi Keerthy,

    I think I’d like use the SRAM is the Cypress CY14V101QS-SF108XI type.
    Does it work in the AM5746 processor?

    Beat Regards,
    Tom Liu

  • Hi,

    We have reached our experts on the particular part compatibility with AM5746.
    We will get back to you in couple of days after analysis.

    Thanks,
    Keerthy

  • Hi Liu,

    Here is the response from the QSPI Expert:

    From HW perspective, this flash should work with AM5746 QSPI controller
    in QUAD mode. However AM5746 QSPI does not support quad mode TX but only
    supports  Quad mode RX (ie Only receiving data from flash is supported
    on all 4 wires)
    
    So, in case of read,cmd and address on single wire, data phase can be single/dual/quad
    
    In case of write,cmd-addr-data are all on single wire (no quad or dual mode support)
    
    Therefore SW should use QOR (0x6B) cmd for read in quad mode.
    But write to flash is always on single wire using WRITE (0x2) cmd
    
    From SW perspective, Implementer would need to modify
    drivers/mtd/spi-nor/spi-nor.c if Kernel <= 5.4  to support
    CY14V101QS-SF108XI flash...
    CY14V101QS-SF108XI follows spansion command set.
    So implementer would need to map this flash to MFR_SPANSION specific quad enable sequence and
    read/write opcode
    
    Note that Linux SPI NOR framework does not take care of AutoSTORE and
    AutoRECALL requirements during power down and powerup. Its upto implementer
    to ensure adequate time (ref flash datasheet) is provided during power
    up for Auto RECALL to complete before accessing flash."
    
    

    Hope this answers your question. If yes please resolve the thread & also the other thread you created:
    https://e2e.ti.com/support/processors/f/791/p/920711/3401202#3401202