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66AK2G12: SPI ADC interface automation to reduce Processor overhead

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Part Number: 66AK2G12

We are planning to use the 66AK2G12 controller, we have some queries on how to reduce the processor overhead without using PRU module, as using PRU will increase our software certification complications.

  1. Is there a way to completely automate the SPI-ADC data collection and store it in DDR RAM memory ? – I understand it is possible to put the SPI as salve and configure the DMA. But is it possible with Processor-SPI as Master ?
  2. There is a feature in SPI called automatic delay feature between transfer (WDEL) which inserts up to 65 clocks of delay between transfers, can that be used to automate the transfers ? If not, what is the purpose of this feature ? If this can automate the data acquisition, how to configure the SPI controller to write/read 8 words of data ?
  3. While using SPI in master mode, how to initiate a read cycle for reading multiple channel information. Eg. say 4 channels with 24-bit each which is 96-bits of data. (8 words, if we configure 12 bit as one word) ?
    1. How the SPI controller will issue clock for reading 96-bits of data ?
    2. Do we need to write 96-bit data to read 96-bit data ? – Looks like the SPI clock generation depends on how many words (2 to 16) we write on SPI.
    3. Does the processor have to poll the SPIEMU register continuously to load the next word in SPIDAT register to read the consecutive data from ADC ?
  4. How can we interface the DMA XEVT & TEVT to external signals ?

Thanks,
Sivakumar.