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TMS320C6657: MCSDK v2.1.2.6 : DDR3 controller configuration

Koichiro Tashiro
Mastermind 21140 points
Part Number: TMS320C6657

Hi,

My customer is using C6657 in legacy product and needs to do some DDR3 debug.

As the software is a bit old one (MCSDK v2.1.2.6), no one at customer knows implementation in details.
Customer wants to know exact source codes where below DDR3 memory controller registers are configured.

Base address: 0x2100:0000   DDR3 EMIF configuration
Offset: 000h to 120h         DDR3 Memory Controller Registers

Could you point me the source file and line# in MCSDK?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru* 95265 points

    Hi,

    First thing is that MCSDK is obsolete, please try to upgrade to PRSDK for C6657 if possible. 

    In the MCSDK application examples, they typically run from no-boot mode assuming the DDR3 is already configured. This is done by GEL file under ccs\ccs_base\emulation\boards\evmc6657l\gel\evmc6657l.gel. This is a single file and searching for ddr3_setup_auto_lvl_1333() you can easily see how the DDR3 is configured.

    If customer use other boot modes, the TI IBL (intermediate boot loader) configures the DDR3 for usage. This is done by: mcsdk_2_01_02_06\tools\boot_loader\ibl\src\hw\ddrs\emif4\emif4.c, starting from line #221:

       else if (v == DEVICE_C6657_JTAG_ID_VAL)

    Regards, Eric