Hi Team,
My customer is wondering:
On the C6654, are there any issues with using the SYSCLKOUT pin (it is connected to SYSCLK7) as a clock so the EMIF16 lines (clocked with SYSCLK7) can be treated as a synchronous bus?
They want to attach the EMIF16 lines to an FPGA and sending the SYSCLKOUT to the FPGA would help with metastability.
Thanks,
Connie