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TMS320C6678: TMS320C6678 DDR3 Clamshell Placement

Shekhar Kulkarni
Intellectual 880 points
Part Number: TMS320C6678

Hi Sir/Madam,

I am using TMS320C6678 along with DDR3 [4 Nos] i.e x64bit Data wide with 666MHz Operating. speed

I have PCB space constraints, So i may not be able to place the DDR3s in flyby topology as per "SPRABI1C"

So can i place these DDR3 in clamshell topology ? 

PS: Anyways we shall carry out Signal Integrity analysis for the same. 

  • 0
    TI__Mastermind 46460 points

    Shekhar,

    We very strongly recommend that you implement the SDRAM all on one side of the board and on the same side as the C6678.  There are many benefits from this implementation regarding routing and via stub management.  Even if you implement SDRAMs both top and bottom, they must appear electrically in a fly-by arrangement without any branching of the ADDR / CMD / CNTRL / CLK routes terminated to VTT.  Customers that attempt SDRAM placement on both sides normally have significant stability issues and have to operate the DDR3 interface at a sub-optimal rate to obtain robust operation.  Also note that simulation of via structures in high performance interfaces like DDR3 are very difficult and often do not correlate with actual signal integrity. 

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 880 points

    HI Tom,

    Thank you for your feedback.

    My one query is, why not Xilinx FPGA's and other NXP Processors do not restrict the usage of Clamshell topology for DDR3/DDR4.

    ANd we have proven even Xilinx Zynq Ultrascale+ DDR4@1600Mbps with Clamshell topology 

    Why TI's processor have such restrictions ?

  • 0 in reply to Shekhar Kulkarni
    TI__Mastermind 46460 points

    Shekhar,

    I cannot explain how these other devices achieve this functionality.  I speculate that these are newer devices that have additional functionality which either requires additional power consumption or are more expensive.

    Tom