• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 101 subscribers
  • Views 212 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

PRU-ICSS-INDUSTRIAL-SW: Controlling of PRU_ICSSG MII_G_RT Module

PRU-ICSS-INDUSTRIAL-SW: Configuration of Inter Packet Gap in "emac" driver (v5)

Debarun Roychowdhury
Intellectual 650 points
Part Number: PRU-ICSS-INDUSTRIAL-SW

Hi,

  I am studying the emac driver (v5) of "pdk_am65xx_1_0_7". I have a query regarding the configuration of Inter Packet Gap during link up.

  Suppose I am using ICSSG2 and one of the port is has auto negotiated to 1Gbps and another port has auto negotiated to 100 Mbps. Now for both the cases "emac_icssg_update_link_params" function in "emac_drv_v5.c" will be invoked. 

  Case 1: 1Gbps

  "emac_icssg_update_link_speed_1G" will be invoked from "emac_icssg_update_link_params" and the "MII_RT_TX_IPG1 Register" will be set to EMAC_ICSSG_CONFIG_TX_IPG_104_NS

 Case 2: 100Mbps


 "emac_icssg_update_link_speed_100MB" will be invoked from "emac_icssg_update_link_params" and the "MII_RT_TX_IPG1 Register"  will be set to "EMAC_ICSSG_CONFIG_TX_IPG_960_NS", thus overwriting the value set in Case 1.

  Is the above behavior expected?

  What is the difference between "MII_RT_TX_IPG0 Register" register and "MII_RT_TX_IPG1 Register " .  By any chance should the code set "MII_RT_TX_IPG0 Register" for port 0 and "MII_RT_TX_IPG1 Register" for port 1?


 It will be really helpful if the above point is cleared.

Best Regards,

Debarun

  

  • 0
    TI__Genius 14680 points

    Debarun,

    Thanks for flagging this. There is a programming sequence needed for the IPGs that we don't have clear in the documentation.

    The hardware only latches the IPG1 register (i.e. the register takes effect) when IPG0 is written.

    So to update IPG0, a write to IPG0 is sufficient.

    To update IPG1, a write to IPG1 followed by a write to IPG0 is required.

    I'll file a request to update the documentation.

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Intellectual 650 points

    Hi Dave,

     Thank you for the reply. It really helps.

      In the emac driver code (v5), I do not find this sequence (write to IPG1 followed by IPG0 write). Does it mean that the inter packet gap set by the emac driver code during link up (only IPG1 is written during link up) does not take effect ?

    And how to set different inter packet gaps for the two ports controlled by the ICSSG?

    Best Regards,

    Debarun

  • 0 in reply to Debarun Roychowdhury
    TI__Genius 14680 points

    Debarun,

    You are correct. I do not see this in the driver either.

    It looks like while the variable includes "ipg1" in the name, it is setting the address for the specific port number being updated. So as long as both ports are matching link speed (and therefore presumably the target IPG) then the setting should be OK for both. But this is incomplete, and the sequence should be improved. I've filed this with the driver team and will confirm the same.

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    TI__Genius 14680 points

    Debarun,

    I have a follow up. We have an update to the EMAC driver implemented, though it didn't intersect with the Processor SDK 7.0 release and will be in the next. You can view/pull the latest from https://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/drv/emac/src/v5/emac_utils.c

    Best regards,

    Dave