Hi,
Our third party has a question/request about ICE connection. Could you answer their question/request below ?
They’re using their own JTAG ICE and could connect to DMSC (Cortex-M3) on AM65x by controlling PWRAP. They’re referring to
https://sourceforge.net/p/openocd/mailman/message/36674568/ and setting as follows;
+ # To access M3, we need to enable the JTAG access for the same.
+ # Ensure Power-AP unlocked
+ $_CHIPNAME.dap apreg 3 0xf0 0x00190000
+ $_CHIPNAME.dap apreg 3 0x50 0x00102098
Since they couldn’t understand the above operation, could you share any document regarding PWRAP with them ?
They referred to 13.3.7 Debug and Device Management in TRM, but couldn’t find the detail description.
Regards,
Hideaki
