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DRA712: [DRA71x_DDR3L] Leveling timeout on EMIF

Part Number: DRA712

Hi Ti,

 

OS: QNX

DDR3L SDRAM : MT41K128M16JT125AIT

I use the DDR tool provided by ti to generate DDR parameters. After configuring DDR parameters, a timeout occurred during DDR initialization.

Related log:

--> init_sdram
chip_revision = 0x2B9BC02F
enter ---- init_dmm
init_emif: DRA71x_DDR3L_666MHz_emif_regs
emif_get_ext_phy_ctrl_const_regs: default
do_ext_phy_settings_dra7: hw_leveling
Leveling timeout on EMIF
dra7_ddr3_leveling: EMIF_STATUS = 0x40000054
HW leveling success

Attached is the configuration of DDR tool and parameters, can you help analyze the reason for the EMIF timeout?

DRA712-EMIF_RC.rar