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TMS320C6678: DDRSLRATE[1:0] ; PTV15

Part Number: TMS320C6678

Hi,

I am going for DDR simulation.

Please advise on what DDR signals the PTV resistor value affect. 

what is the slew rate for different DDRSLRATE[1:0] settings? on what signal it affects? 

Erez.

  • Erez,

    The turn-on slew rate of all DDR output signals is programmed using the slew rate control pins DDRSLRATE[1:0]. Please note that these pins DO NOT effect the driver DC drive-strength. They only control the driver turn-on time.  Therefore, these pins are not expected to change the slew rate of the transmitted signals.  They provide a control to the buffer turn-on that has impact on the power supply noise generated during this switching.  The output buffer drive strength is tied off to a fixed value.

    The PTV15 resistor recommendation is in the DM:

    A precision resistor placed between the PTV15 pin and ground is used to closely tune the output impedance of the DDR interface drivers to 50 ohms.  Presently the recommended value for this 1% resistor is 45.3 ohms.

    We do not recommend that the value of this resistor be changed.  This is the value used for all simulations and validation..  Please refer to section 6.5.1 of the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1C) for an explanation of how the PTV15 resistor sets the PHY drive strength and the PHY-side ODT impedance.

    Tom