TDA2SX: TDA2SX: How to config DSS Vout1 output BT656 YUV422 8bit with external syncs?

Hi Wade,

Please refer to the application node: https://www.ti.com/lit/an/sprac16a/sprac16a.pdf.

The same mechanism is used to get YUV over separate sync output. You could need to treat input YUV as RGB565 and get the RGB565 output over 8bit interface and that's how you could get BT601 output from TDA device.

Regards,

Brijesh

Hi Brijesh,

    In vps code of starterware, we only found three DVOFMT as below,

 typedef enum
{
    VPS_DCTRL_DVOFMT_BT656_EMBSYNC = 0,
    /**< Output data format is BT656 with embedded sync */
    VPS_DCTRL_DVOFMT_BT1120_EMBSYNC,
    /**< Ouptut data format is BT1120 with embedded sync */
    VPS_DCTRL_DVOFMT_GENERIC_DISCSYNC,
    /**< Output data format is for any discrete sync */
    VPS_DCTRL_DVOFMT_MAX
    /**< This should be the last Enum */
} Vps_DctrlDigitalFmt;

In function halDispcOvlyBT656_1120Conf() of vpshal_dssDispcOvly.c file, if the high level set DVOFMT to DISCSYNC, the BT656 enable bit will be set to 0. 

        regVal = HW_RD_REG32(dispcOvlyObj->regOffset.dispcConfig);
        HW_SET_FIELD32(
            regVal,
            DSS_DISPC_CONFIG1_BT656ENABLE,
            0U);
        HW_SET_FIELD32(
            regVal,
            DSS_DISPC_CONFIG1_BT1120ENABLE,
            0U);
        HW_SET_FIELD32(
            regVal,
            DSS_DISPC_CONFIG1_CPR,
            0U);
        HW_SET_FIELD32(
            regVal,
            DSS_DISPC_CONFIG1_COLORCONVENABLE,
            0U);
        HW_WR_REG32(dispcOvlyObj->regOffset.dispcConfig, regVal);

wade

Wade,

Yes, that's correct. DVOFMT should be set to generic discrete sync output format and in that case, BT output will be disabled.

Rgds,

Brijesh

Hi Brijesh,

   Does that mean the DSS can't work on BT656 output with discrete sync? The discrete sync mode is only used for RGB888, RGB565 output?

wade

Hi Brijesh,

     Is it possible use DSS to output YUV4:2:2 8-bits? In file "DSS Bit Exact Output " ,? We only found how to config DSS to output RGB888 or RGB565 via 8-bit data lines with discrete syncs, not found anything for outputting YUV4:2:2  via 8-bit data lines with discrete syncs.

   If yes, could you please tell me how to config?  Thanks a lot!

wade

Hi Wade,

Yes, it is possible. But this requires to bypass/disable all pixel processing modules in video pipelines as well as in overlay manager.

You could store data in YUV422 format, but configure DSS video pipeline in RGB565 format. Then in overlay manager, disable blending and enable TDM module to send out RGB565 module over 2 clock cycles over 8bit interfce.. This way, you could YUV422 over 8bit discrete sync interface.

Rgds,

Brijesh

Hi Brijesh,

   Thanks! I see, but it seems not easy to do. Do you have any demo for it?

wade

Hi Wade,

Unfortunately, there is no demo. There are just few APIs that needs to be taken care.

Rgds,

Brijesh  

Hi Brijesh,

    Thanks for your quickly response! Could you please list the related registers we need modify?

wade

Hi Brijesh,

     We have another question about YUV422 output. 

     Does the DSS can output YUV4:2:2 8-bits on DDR mode? That means the Y data output when pixel clock is rising edge, the U/V data output when pixel clock is falling edge. 

wade

Hi Brijesh,

Any update?

Hi Wade,

DSS does no support DDR output format. It supports only SDR mode. 

Let us know if there are any further questions.

Regards,

Brijesh