Hi export,
I'd like to know the number of minimum input voltage of SGMII0RXN (ball AE2) and SGMII0RXP (ball AE3).
Where is it described?
Thanks and Best regards,
HaTa.
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Hi export,
I'd like to know the number of minimum input voltage of SGMII0RXN (ball AE2) and SGMII0RXP (ball AE3).
Where is it described?
Thanks and Best regards,
HaTa.
HaTa,
The SGMII interface on the C6655 is a SERDES interface. These are not specified like LVCMOS digital pins. Please see the statement copied below from the Data Manual (SPRS814):
6.15.3 EMAC Electrical Data/Timing (SGMII)
The Hardware Design Guide for KeyStone Devices specifies a complete EMAC and SGMII interface
solution for the C665x as well as a list of compatible EMAC and SGMII devices. TI has performed the
simulation and system characterization to ensure all EMAC and SGMII interface timings in this solution
are met; therefore, no electrical data/timing information is supplied here for this interface.
The Hardware Design Guide for KeyStone Devices (SPRABI2) then provides more information in section 6.4:
6.4 Ethernet
Documentation for EMAC:
• KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User's Guide
• SGMII Specification (ENG-46158), Version 1.8, dated April 27, 2005 [7]
• SerDes Implementation Guidelines for KeyStone I Devices
This section then continues and provides implementation details specific to SGMII on this device.
The referenced User's Guide (SPRUGW1) provides detailed implementation about the software for the SGMII interface.
Additional SERDES-specific hardware guidance is provided in the referenced SerDes Implementation Guidelines (SPRABC1) in Chapters 2 and 6.
Chapter 6 then lists this electrical standard for complaint signal levels:
6.1 Relevant Industry Standard Specification Support
The SGMII interface adheres with IEEE Standard for low-voltage differential signals
(LVDS) for Scalable Coherent Interface (SCI) IEEE1596.3-1996.
Tom
Hi Tom,
>The Hardware Design Guide for KeyStone Devices specifies a complete EMAC and SGMII interface
> solution for the C665x as well as a list of compatible EMAC and SGMII devices.
Where can I see the device list which is compatible with C665x. I cannot find it.
Thanks and Best regards,
HaTa.
HaTa,
I am not sure that I understand the question. Are you asking for a list of compatible devices for connecting SGMII to the C665x DSPs? If so, we do not provide such list. Any SGMII compliant device is compatible. You should implement series capacitors on the SGMII links but that is the only requirement.
Tom
Hi Tom
Thanks for giving me your feedback!
I'm referring the following description which you on this thread before,
>6.15.3 EMAC Electrical Data/Timing (SGMII)
>The Hardware Design Guide for KeyStone Devices specifies a complete EMAC and SGMII interface
>solution for the C665x as well as a list of compatible EMAC and SGMII devices. TI has performed the
>simulation and system characterization to ensure all EMAC and SGMII interface timings in this solution
>are met; therefore, no electrical data/timing information is supplied here for this interface.
I understand the contents of above as follows.
Instead of providing the electrical data/timing information, TI provide the list of compatible EMAC and SGMII devices which TI has performed the simulation
and system characterization.
Therefore, I asked a question like the last time.
"Where can I see the device list which is compatible with C665x. I cannot find it."
Thanks and Best regards,
HaTa.
HaTa,
That comment in the Data Manual is overstated. We cannot recommend specific devices at other semiconductor companies. Instead, we provide guidance to allow our customers to identify and select compatible devices. That is why the Hardware Design Guide provides the following information:
6.4.2 System Implementation of SGMII
SGMII uses LVDS signaling. The KeyStone I device uses a CML-based SerDes interface that requires AC
coupling to interface to LVDS levels. Texas Instruments recommends the use of 0.1-μF AC coupling
capacitors for this purpose. The SerDes receiver includes a 100-Ω internal termination, so an external
100-Ω termination is not needed. Examples of SerDes-to-LVDS connections appear in the following
sections.
If the connected SGMII device does not provide common-mode biasing, external components need to be
added to bias the LVDS side of the AC-coupling capacitors to the nominal LVDS offset voltage, normally
1.2 V. Additional details regarding biasing can be found in Clocking Design Guide for KeyStone Devices.
For information regarding supported topologies and layout guidelines, see the SerDes Implementation
Guidelines for KeyStone I Devices .
The SGMII interface supports hot-swap, where the AC-coupled inputs of the device can be driven without
a supply voltage applied.
SRIO/SGMII SerDes power planes and power filtering requirements are covered in Section 7.3.
As long as you select a compatible part and design the board such that the signals comply with the SGMII Specification (ENG-46158), Version 1.8, dated April 27, 2005, this is sufficient to ensure that the implementation will be robust.
Tom