Compiler/DRA829V: PCIe's pins on DRA829 EVM

Jia Hong, 

I MDIO pins you mentioned are to communicate with the DP83867 PHY off the MCU_RGMII. That should be be related to what you need for the PCIe NIC. 

On your question:

   >>I want to get the pins related with MDIO of "PCIe x 2 LANE" to operate MDIO functions.

could you clarify what are you trying to achieve? I understand your PCIe card is a network interface card, so it behaves like Ethernet ports to the kernel. But I assume the MDIO functions are emulated via PCIe traffic, or you need dedicated GPIO/MDIO pins? i.e., the kernel does not communicate with the PHY directly in this case. 

Pls let me know if i missed anything about your card.

regards, 

Jian 

Hi Jian,

Our device is able to be regarded as the I2C/MDIO client controlled with the I2C/MDIO master.
In the current status, TI's platform is regarded as the I2C/MDIO master.

Q: Why did we use the pins related with MDIO of "PCIe x 2 LANE"?
A: The pins are used the jumper wires to connect to our demo board easily. It is nothing to do with Ethernet packet traffic (e.g. RGMII, etc.).

If this method is not feasible, do you have any better suggestions?

Best Regards,
Jia Hong

Jia Hong,

There are additional MDIO pins in the main domain, that may be better suited for what you need. From your answer, I was not clear if you need simultaneous I2C and MDIO (total of 4 pins) masters on the SOC, or you just want to connect two pins then use jumper switch to switch between I2C/MDIO modes? Even in later case, I do see MDIO0 pins off he main domain. These pins are also muxed with GPIOs, so you may use software to control pinmux and function. 

I just check device tree files but was not able to find MDIO entries, it may be in the "Quad-Ethernet expansion card" device tree overlay. let me know if you need further help to find the device tree, i can check with the driver team.

Jian 

Hi Jian,

We want two modes (I2C and MDIO) in our cases.
From the TI's specification, is it working if we use the pins as the attachment's information?

Best Regards,
Jia Hong

Hi Jian,

If we use J46 to operate MDIO and I2C, what should we do in addition to modify the device tree?
Moreover, how do we change the device tree? Any standard operation procedure?

Jia Hong

Hi Jian,

Sorry. One more question.

Are the following pins working for RGMII on J46? Is the implementation the same as  MDIO and I2C?



Jia Hong

Jia Hong, 

PRGx_RGMII pins are driven by the ICSSG firmware. Could you clarify in your last question - are you trying to use those RGMII ports, or just want to use the MDIO pins? These MDIO pins are intended for ICSSG firmware to control PHYs directly. So there will not be driver support unless you unable ICSSG firmware. 

Back to J46, it seems pins 97 and 99 is the MDIO the port you needed. I see they are on A29-30 of the  x1Lane PCIe slot (J11). So our intention is to modify the device tree so use the MDIO pins to configure PHYs on the PCIe card? please confirm my understanding. 

Documentation on device tree is scattered, so you will have to reference to the CPSW2G driver section of the SDK user guide (Sec 3.2.2.6) for generic MDIO support. For MDIO in the main domain, I saw the CPSW9G need to be called via R5F firmware. So need to check with the team on if there is standalone MDIO driver. That would be ideal. 

Let me know if I misunderstood any of your intentions. 

Jian 

Hi Jian,

Our solution is that we design an adapter board or a connector to connect our board with the TI platform.
The connecting interface is J46. There are 3 interfaces (I2C/MDIO/RGMII) on the connector.
We hope that the connector will be working normally. Therefore, we want to get your suggestions.
The information on the TI website is so scattered, so we want to the simple SOP for modify the device tree or driver to shorten the development time.

Thanks a lot.

Jia Hong

Update from offline email discussions, we confirmed (J46) with below pins available for CPSW9G. 

Additional conversations in offline email are regarding to software bring up of customer board. 

Will keep this ticket open till MDIO clarified. 

jian 

From: Wang, Jian <jian-wang@ti.com>
Sent: Friday, September 11, 2020 11:23 PM 

Jia Hong,

I checked pinmux (not sure if you already used – you can download the pinmux tool from the DRA829 product folder), it seems that the 4 RGMII ports are muxed between ICSSGx and CPSW9G.  Specifically:

• PRG0_RGMII2 muxed with CPSW9G_RGMII4
• PRG0_RGMII1 muxed with CPSW9G_RGMII3
• PRG1_RGMII2 muxed with CPSW9G_RGMII2
• PRG1_RGMII1 muxed with CPSW9G_RGMII1
• MDIO0 is on the J46 (they are also on the x1lane PCIe slot)
• Both I2C0 and I2C1 ports are available on the J46 also.

The common Processor board schematics did not show the RGMIIx pins, where only the PRGx_RGMIIx port pins are show. But you can configure to use CPSW9G to drive those pins. You may want to double check using the pinmux tool:

• Select CPSW9G as the controller
• Choose RGMII1,2,3,4 sequentially, make sure all 12 pins of each RGMII ports are available on the J46. You can highlight the green dots on the chip diagram to have the primary pins names shown.