CHIP_CLK1 is used for many clocks (GPMC_FCLK = CHIP_CLK1/3, EMIF_DDR = CHIP_CLK1/2 and so on).
How is the CHIP_CLK1 derived by PLL controller ?
There is no dscription of CHIP_CLK1 in the Figure 5-166. MAIN PLL and PLL Controller and Figure 5-167. PLL and PLL Controller Generic Block Diagram of Technical Reference Manual.
Where can I learn it?