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66AK2G12: RESET OF EVMK2GX in the schematic

Part Number: 66AK2G12
Other Parts Discussed in Thread: EVMK2GX

Accroding to the schematic of EVMK2GX in the sheet 10, there are three RESET signals (FULL RESET, WARM RESET and POWER ON RESET.)

What is the difference between these RESET? Why thsse are separated? What is the intent?

It would be helpful if you had any explanation.

Thanks.

  • Hi,

    See section 4.2.2.1.1 and section 5.3 of the 66AK2Gx Multicore DSP + ARM Keystone II System-on-Chip (SOC) TRM (Rev. I) for information on the resets.

    Regards, Bill

  • Hi Bill,

    I don't understand the difference between the PORn pin and RESETFULLn pin although I read section 5.3.2 of TRM.

    The section 5.3.2 of TRM says "HHV logic enforces this requirement when PORn is active (low)." and

    "Asynchronous logic enforces this requirement when PORn is inactive (high) and RESETFULLn is still active (low)."

    What's the Asynchronous logic?  Why PORn and RESETFULLn must be the different signal?

    Is there any problem if PORn and RESETFULLn are the same signal?

    Thanks,

    Fujii

  • Hi

    What does 'Asynchronous logic' refer to? 

    "Asynchronous logic enforces this requirement when PORn is inactive (high) and RESETFULLn is still active (low)." in the section 5.3.2 of TRM.

    Thanks.

  • Hi Fujii,

    PORn and RESETFULLn have almost the same function inside the device.  There are two signals because we decided to provide a separate input for the power on reset function and a system controlled cold reset. 

    The PORn is the typical power on reset that is used to hold the part in reset while the power supplies are stabilizing and the clock is starting.  The HHV logic controlled by the PORn will keep the IO buffer cells in a state designed to tolerate the environment where the IO supply voltages are ramping.  If a single cold reset is used in your system it should be PORn.

    The RESETFULLn is also a cold reset but it does not trigger the HHV logic.  It uses asynchronous logic to ensure that the device is reset correctly even if the clock is not present for the entire reset pulse.  Note that the clock must be present for the appropriate time before either the PORn or the RESETFULLn signals are released. 

    All TI processors have a PORn power on reset that ensures the device is in the default state once the power supplies have stabilized.  The RESETFULLn input was added to simplify the addition of a cold reset triggered by logic and it is intended to be used while the power supplies remain stable. 

    Regards, Bill

  • Hi Bill

    Thank you for teaching me so kindly.

    We only cares about single cold reset. Then, which can you recommend, RESETFULLn is pull-up (invalidation) or RESETFULLn is connected to the same signal as PORn?

    Thanks.

    Fujii

  • Hi Fujii,

    If a single reset is used you should use the PORn signal. The RESETFULLn can be pulled high.

    Regards, Bill