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AM5748: Interrupt mapping for sys_nirq1 pin

Snehal Patel58
Intellectual 810 points
Part Number: AM5748

Hi All,

We are using the latest processor sdk linux for am5748 sitara,

we have connected an interrupt line for an external device to sys_nirq1 pin, when we try to register the interrupt handler in the Linux driver we are seeing errors,

at u-boot this pin is mixed of interrupt functionality.

ret = request_irq(2, &z85_isr, IRQF_TRIGGER_FALLING, "Zilog", sad); // EXT_SYS_IRQ_1 == MPU_IRQ_7 == 2

[ 136.799349] Z85: request irq, num=0x2
[ 136.803080] fail to request_irq for irq num = 2
[ 136.807671] Z85: request irq, ret=0xffffffea

for the TRM this sys_nirq1 is mapped to MPU_IRQ_7:

TRM Page num:4239 Table 18-2. MPU_INTC Default Interrupt Mapping 
"MPU_IRQ_7 (ID39) 2 CTRL_CORE_MPU_IRQ_4_7[24:16] 2 EXT_SYS_IRQ_1 External interrupt (active low) via sys_nirq1 pin"

but when we convert to gpio and do gpio_to_irq we are able to register isr handler.

isq = gpio_request(GPIO1_3, "irq_rx");
if( (isq = gpio_to_irq(GPIO1_3)) < 0 ) return -1;

is there any difference if we map irq using gpio_to_irq then directly irq number?

if yes, then how we can map this irq to isr handler(directly using irq number without converting to gpio.

Regards,

Snehal

  • 0
    TI__Guru*** 125430 points

    Snehal,

    In my opinion, it is better to map this pin as a gpio and correspondingly use the gpio interrupt.  The reason for this is because there are additional requirements that are imposed if you are using the pin as sys_nirq.  There is handshaking that occurs "under the hood" for most interrupts.  For example, when a GPIO interrupt occurs, the GPIO peripheral keeps the internal interrupt signal asserted until the ISR has acknowledged the interrupt at the peripheral.  If you use the sys_nirq pin then that handshaking becomes your responsibility.  In other words, edge-based interrupts are not allowed with sys_nirq.  It is strictly level based.  Furthermore, your external device must keep that interrupt asserted until it has been acknowledged in the ISR (e.g. you would need a sideband like SPI/I2C to acknowledge the interrupt and tell the device to de-assert it).

    Best regards,
    Brad