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AM3354: RGMII V2 spec

Garret Holt
Intellectual 1050 points
Part Number: AM3354

Hello Team,

We are working with AM3354 in an application that requires 2 ethernet ports and will be taking advantage of the two integrated 1G MAC RGMII interfaces. Do these interfaces support the RGMII v2 spec of 1.2ns delay between CLK and data? Not seeing this mentioned in the datasheet. Thank you!

Regards,

Garret 

  • 0
    TI__Guru*** 125430 points

    Garret,

    Let's look at receive and transmit separately:

    • Receive: The AM335x requires the PHY to delay the clock 1.2ns.  This can be seen in Table 7-19 which shows a 1ns setup time for the data.  This is further emphasized by footnote A which states: "RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the respective timing requirements."
    • Transmit: The AM335x does not delay the clock. This can be seen in Table 7-21 which shows the TD to TXC output skew as being +/-0.5ns. Footnote A further emphasized this point by stating "the AM335x device does not support internal delay mode."

    Best regards,
    Brad