Hi,
I didn't see it in the datasheet, what is it the PPM clock requirements for the inputs clocks?
for: SGMIICLK input clock and others :
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Hi,
I didn't see it in the datasheet, what is it the PPM clock requirements for the inputs clocks?
for: SGMIICLK input clock and others :
Shay,
Please refer to chapter 3 in the Hardware design guide for KeyStone I devices Application Report (SPRABI2). It has the information required for the SERDES clocks.
Tom
Thanks,
where can I find the ddr3 layout guidelines?
I saw the "DDR3 Design Requirements for KeyStone Devices" but I didn't find what is the rules of spacing between the signals group, for example what is the spacing that I need to save in the layout between the data line inside the data group (D0,D1,D2...D7)?
Shay,
Please also see the KeyStone™ I DDR3 interface bring-up Application Report (SPRACL8) for a summary of all DDR information available.
Tom
Tanks,
I read the 6.3 section and SPRACL8 but I didn't see reference to the spacing between the signals in the group.
I only saw in 6.3.1.3 that
"
Center-to-center spacing, including serpentine, must be at least 5 W where W is the trace width.
Additional spacing can be added between differential pairs and other routing groups to minimize
crosstalk. Spacing of 4 W can be used, but is not appropriate for bus speeds over 1066 MT/s.
"
But it is not specified whether the reference is to the spacing between the groups (address/data/control) or to the spacing between the signals inside the group (for example data group signals)
Shay,
That was the guidance provided for this old device. It did not differentiate spacing within the routing groups and between signals in different routing groups. If you look at the DDR layout for the C6678 EVM, you will see that the entire interface is routed using 5W spacing.
Tom