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[FAQ] 66AK2H14: How to modify Keystone-II DDR configuration

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Part Number: 66AK2H14

When developing on a custom board, we recommend following the Custom Board Porting Guide (linked below) in the Processor Software Development Kit  (PSDK) which highlights the key considerations of creating a custom board library.

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#custom-board-addition 

PSDK contains module initialization and register configuration for the DDR memory on the TI evaluation platform. If developing on a custom board with a different external memory, please refer to the “Useful DDR configuration resources” section (linked below) in the PSDK documentation which links to various useful application notes and tools for DDR configuration on different processors.

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/FAQ.html#useful-ddr-configuration-resources

Specifically for Keystone-II family of devices, we recommend referring to the Keystone II DDR3 Initialization Application Note . This app note provides a step-by-step initialization guide, a spreadsheet tool that helps compute the values for the on-chip DDR3 controller, and links to other relevant DDR3 collateral.

For Linux users, Processor SDK U-Boot code reads DDR3 SPD info to initialize DDR3 by calling ddr3_init_ddrphy() and ddr3_init_ddremif(). Based on the SPD info, init_ddr3param() sets the PHY and EMIF register values accordingly, and passes them to ddr3_init_ddrphy() and ddr3_init_ddremif(). If SPD info isn’t available, the DDR3 vendor should have PHY and EMIF configuration info and the values can be computed from the spreadsheet mentioned in Keystone II DDR3 Initialization application note. The PHY and EMIF configuration parameters should replace those set in init_ddr3param().

For Keystone-II devices, this can be done by defining the structures of PHY and EMIF registers as in boot/board/ti/ks2_evm/ddr3_cfg.c. The PHY and EMIF configuration structures are used to configure DDR3 as the sample code below:  

        ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);

        ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);

 

  • This post describes the steps to configure KS2 DDR3

     

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