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66AK2G12: Power-up Sequence - time slot from launch of 3.3V to launch of 1.8V, 1.35 V and 1.0V

Part Number: 66AK2G12

Hi,

According to the "Figure 4. Power Sequencing of TPS65911A User's Guide for 66AK2G12 Processor"

the time slot from launch of 3.3V to launch of 1.8V, 1.35 V and 1.0V is 2~5ms.

If this time slot is 12~28ms, is there any problem?

We are considering implementation with discrete power supplies and TPS3808G01 on behalf of PMIC.

The delay time of TPS3808G01 is 12ms~28ms.

 

Thanks.

  • Hi,

    The document you referenced provides the power sequencing timing for the PMIC, not for the 66AK2G12.  The data manual for the 66AK2G12 provides the sequence but doesn't include specific timing for the delay between power supplies.  The K2G has been implemented with a discrete power supplies without any adverse effect.  Powering only a portion of the K2G can stress the device so we do not allow partial powering, but 12ms to 28ms delay between rails should be acceptable. 

    Regards, Bill