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66AK2H12: ERROR -233 (0xFFFFFF17) while connecting to the Processor

Part Number: 66AK2H12

Hi team,

I am facing below issue when i connect XDS110 JTAG and run test connection 

This error is generated by TI's USCIF driver or utilities.

The value is '-233' (0xffffff17).
The title is 'SC_ERR_PATH_BROKEN'.

The explanation is:
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken
with a stuck-at-ones or stuck-at-zero fault.

Please can anyone help me out how to solve this.

I have gone through all the previous links and tried the methods suggested by those links.

Please let me know how to proceed further?

Regards,
Karthik

  • Hi, Karthik,

    Do you mean that you run the USCID driver code and you get this 233 error? Could you indicate where the USCIF code/example is located?

    For error code 233, please see explanation in "Debugging JTAG". 

    software-dl.ti.com/.../ccs_debugging_jtag_connectivity_issues.html

    Rex

  • Hi Rex,

    Let me make few things clear, so that you can narrow down to the issue soon.

    We have 14 numbers of same PCB and in 13 boards there is no issue observed and all the interfaces are working and we are using the working/same utility  drivers to and working emulator/JTAG probe to connect to the processor but we  are getting the above issue.

    So suspecting board layout or software drivers that are used would not help us, since we are using the proven design.
    We have probed all the lines in which we observed that TDO is not at all responding.

    Is the processor broken? If there is any physical damage has happened how to confirm that?

    I am currently stumped. Any ideas as to what I can look into or test to help diagnose my problem?

    Regards,
    Karthik

  • Hi,

    So this is your own board with XDS110 emulator, 13 out of 14 worked. What is the JTAG clock speed? For the failure one, will it work with lower TCLK?

    Regards, Eric 

  • Hi Eric,

    Thanks for your response.

    The JTAG clock frequency is 2.5MHz.
    we have also probed the clock in scope and its neat and clean.
    Yes we tried reducing the JTAG clock frequency to the minimum i.e; 100KHz and ran test connection but we encountered the same the same error.
    Is there any particular minimum voltage that we can set and run test connection. Please suggest.

    Regards,
    Karthik

  • Hi Karthik,

    JTAG I/Os should be 1.8V on this part.  Do you see any application-level indications that the device itself is running when you encoutner this problem? For example, if your system toggles LEDs to indicate different phases of operation then are you seeing that function properly?

    As noted this error message indicates that the JTAG scan chain appears to be broken. A few things that you can review:

    1] Probe JTAG interface near device (TCK, NTRST, TDI, TDO, TMS) during JTAG activity (which can be provoked using the "Test Connection" button in CCS). During JTAG activity you should observe:
    i] TCK should be toggling (either freely or only during JTAG activity--depends on XDS capabilities)
    ii] nTRST should be HIGH (though you may see it pulse low early on)
    iii] TMS/TDI should change state frequently
    iv] TDO should change state

    2] If you see all of the above happen except for TDO changing state then you should review the state of the device resets (but this is likely only going to be an issue if the system is otherwise not functioning as expected):
    i] Verify the device is being reset properly
    ii] Verify that POR sources (e.g. PORz and RESETFULLz pins) are not active during JTAG scan
    iii] Verify that the device is out of reset during JTAG scan (RESETSTATz pin should be HIGH)

    --Jason