Hi,
In TMS320C5517 demo board, CLKSEL = 1, CLKIN = 12MHz, We find from the EVM5517.gel file:
#define CLKCFGMSW 0x1c1f
#define PLL_CNTL1 0x1c20
#define PLL_CNTL2 0x1c21
#define PLL_CNTL3 0x1c22
#define PLL_CNTL4 0x1c23
#define CLKOUT_CFG 0x1c24
and ProgramPLL_175Mhz_clksel:
// bypass PLL
*(short *)CLKCFGMSW@IO = 0x0;
*(short *)PLL_CNTL1@IO = 0x3956;
*(short *)PLL_CNTL2@IO = 0x0003;
*(short *)PLL_CNTL3@IO = 0x0010;
*(short *)PLL_CNTL4@IO = 0x0020;
// Wait several cycles for the PLL to lock
for(i=0;i<20000;i++);
// Switch to PLL clk
*(short *)CLKCFGMSW@IO = 0x1;
I don't konw why PLL_CNTL3(PCR) =0x10 ? PLL_CNTL3 bit12~0 is reserved according to SPRUH16B, but here set bit4 = 1; Normal operation mode?
Best Regards,
Dudechao