Hi All,
Please see we are using our custom board based on sitara AM3359 processor(reference design from EVM ICEv2),
Currently our board has two SPI interface in which McSPI0 is connected with FPGA. Here McSPI0 acts as Master and FPGA SPI acts as a slave.
Also from u-boot commands (sspi), we are able to transfer data between processor & FPGA, However as mentioned in datasheet & as per our understanding,
Functional clock is observed to be 48 MHz but while probing we observed that transection is happening at 800khz, Here we are not sure how this 800khz conversion is happening.
Furthermore, Dealing with config register ( MCSPI_CH0CONF - 12Ch; McSPI channel 0 configuration register), bit 2-5, No change were reflected in oscilloscope while probing.
Could you please let us know, how to deal with the slave clock for McSPI ?How to change the SCLK of McSPI ?
Awaiting Reply,
Thanks & Regards,
Chinmay