• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 101 subscribers
  • Views 244 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678: DDR3 initialization sequence

Koichiro Tashiro
Mastermind 21140 points
Part Number: TMS320C6678

Hi,

I got a question from my customer about DDR3 initialization sequence.
According to SPRUGV8E.pdf, section 2.11.1 “DDR3 Initialization Sequence”, the initialization sequence is triggered if SDRAM_TYPE=0x3 and INITREF_DIS=0.
Then the sequence follows the JEDEC standard.
According to the JEDEC standard (JESD79-3F), the initialization sequence are below steps;
1) Asserting RESET# signal to L.
2) CKE is pulled to L.
3) RESET# is released.
4) Wait for 500usec until CKE become active
       :
       :

Question:
The DDR3 initialization sequence performed by DSP DDR3 controller is starting from the step#1(i.e. driving RESET# to L) above?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru*** 125430 points

    Koichiro Tashiro said:
    According to the JEDEC standard (JESD79-3F), the initialization sequence are below steps;
    1) Asserting RESET# signal to L.
    2) CKE is pulled to L.
    3) RESET# is released.

    These 3 steps are part of the processor's power-up sequence.  The DDR3 controller asserts RESET# during power-up.  Once its internal reset is released it correspondingly brings RESET# high.

    Koichiro Tashiro said:
    The DDR3 initialization sequence performed by DSP DDR3 controller is starting from the step#1(i.e. driving RESET# to L) above?

    Step 4 is where the process begins.  Steps 1-3 were handled via the power-up sequence.

  • 0 in reply to Brad Griffis
    TI__Mastermind 21140 points

    Hi Brad,

    Thanks for your reply.
    So RESET# is already released when DDR3 controller is configured by user software.

    In SPRABL2E.pdf (Keystone I DDR3 Initialization) Example. 9,
    DDR_SDRFC register is configured to use longer refresh interval to meet the 500us initial CKE=L period.
    Then actual DDR3 controller operation will be started after 500usec with Auto Refresh command, provided user software waits for 600usec in loop(Example 17), correct?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 21140 points

    Hi Brad,

    I got additional questions from my customer.
    Could you answer below ones as well?

    - After the processor’s power-up sequence (RESET# is released),
    DDR controller keeps RESET#=H, CKE=L until user software writes SDRAM_TYPE=0x3 and INITREF_DIS=0, correct?

    - According to JEDEC specification, CK/CK# must be started and stabilized before CKE goes H.
    Is this managed by DDR controller after writing SDRAM_TYPE=0x3 and INITREF_DIS=0 ?
    Or CK/CK# are started and stabilized earlier?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru*** 125430 points

    Koichiro Tashiro said:
    - After the processor’s power-up sequence (RESET# is released),
    DDR controller keeps RESET#=H, CKE=L until user software writes SDRAM_TYPE=0x3 and INITREF_DIS=0, correct?

    Yes.

    Koichiro Tashiro said:
    - According to JEDEC specification, CK/CK# must be started and stabilized before CKE goes H.
    Is this managed by DDR controller after writing SDRAM_TYPE=0x3 and INITREF_DIS=0 ?
    Or CK/CK# are started and stabilized earlier?

    The clock starts as part of the power-on sequence.

  • 0 in reply to Brad Griffis
    TI__Mastermind 21140 points

    Hi Brad,

    Thanks!
    This item is closed.

    Thanks and regards,
    Koichiro Tashiro