I am using K2G ICE board. The default clock speed for ARMSS is 600MHz. According to the specification, this clock speed can be increased up to 1000MHz. We have tried the following two methods, but none of them have worked.
- Called the monitor function _romtConfigPll(UINT32 pllNum, UINT32 prediv, UINT32 mult, UINT32 postdiv)
, which is mentioned in spruhy8i.pdf->Table 4-35. Calls to ARMSS BootROM Functions. I have called this function from the SBL, at the end of SBL_socInit() with the parameters, pllNum = 4, prediv = 1, mult = 40, postdiv = 1, the function returned 0. But I have checked the clock speed and it is still 600MHz. - In another method, we have changed the content of C:\ti\pdk_k2g_1_0_16\packages\ti\board\src\iceK2G\iceK2G_pll.c
/* Earlier content */
: const pllcConfig pllcConfigs_extClk[] = { {CSL_PLL_SYS, 96, 1, 4}, /* 600 MHz */ {CSL_PLL_NSS, 240, 3, 2}, /* 1000 MHz*/ {CSL_PLL_ARM, 96, 1, 4}, /* 600 MHz*/ {CSL_PLL_DDR3, 128, 1, 16}, /* 200 MHz*/ {CSL_PLL_UART, 767, 5, 10}, /* 384 MHz*/ {CSL_PLL_DSS, 190, 12, 16}, /* 25 MHz*/ {CSL_PLL_ICSS, 240, 3, 10} /* 200 MHz*/ }; : /* Now */ : const pllcConfig pllcConfigs_extClk[] = { {CSL_PLL_SYS, 96, 1, 4}, /* 600 MHz */ {CSL_PLL_NSS, 240, 3, 2}, /* 1000 MHz*/ {CSL_PLL_ARM, 40, 1, 1}, /* 1000 MHz*/ {CSL_PLL_DDR3, 128, 1, 16}, /* 200 MHz*/ {CSL_PLL_UART, 767, 5, 10}, /* 384 MHz*/ {CSL_PLL_DSS, 190, 12, 16}, /* 25 MHz*/ {CSL_PLL_ICSS, 240, 3, 10} /* 200 MHz*/ }; :
Could you please suggest how to change the clock speed?