AM4372: WDT works faster than the setting

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Replies: 14

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Part Number: AM4372

Sitara Support Team,

My customer is facing that the WDT operates about 20% faster than the set time
on the custom board with AM4372.
When set to 10 seconds, it activates in 8 seconds, and when set to 20 seconds, it activates in about 16 seconds.

To measure the operation time, the LED mounted for debugging is turned on at the timing to enable WDT,
and the time until reset (LED off) is measured with a stopwatch.

The source clock and register settings seem to be fine.

Could you please point which registers he needs to check?
Is it possible to measure the actual WD Timer Clock Signals; PI_OCP_CLK and PI_SYS_CLK
because they are internal clocks?

Best regards,
Kanae

14 Replies

  • There are two possible clock sources for the WDT – The CLK_RC32K and the CLK_32KHZ. I assume you are using the CLK_32KHZ?

    The selection is made using the PRCM_CM_DPLL_CLKSEL_WDT1_CLK register. Default (reset) is CLK_32KHZ. Check this is register is programmed correctly.

    CLK _32KHZ is derived from the PER_CLKOUT_M2. This would yield 192MHz/8/732 (32.78689Khz) when running at OPP100. There is a different device ration when running OPP50. The divide ration is selected using the register CTRL_CLK32KDIVRATIO. The default (reset) is OPP100. Check that this register is programmed correctly. Of course, the assumption here is that you are running OPP100.

    You can check the PER_CLKOUT_M2 frequency by routing the clock to the CLKOUT2 Pin. Figure 2-20 in the TRM will show you the routing and the registers used to control this. Don’t forget to set the pinmux for pin C24.

    If this is ok, what WDT register settings are you using?

  • In reply to PaulM:

    Hi PaulM,

    Thank you for your reply.

    The status of my customer is as follows.

    ========================================================
    The 32kHz clock that serves as the source is generated internally,
    and the external XTAL is 24MHz.
    The oscillator for the RTC is not used.

    WDT Register setting values;

    0x0000 WDT_WIDR 0x0000 0000 Read Only
    0x0010 WDT_WDSC 0x0000 0010 0x0000 0010
    0x0014 WDT_WDST 0x0000 0001 Read Only
    0x0018 WDT_WISR 0x0000 0000 0x0000 0000
    0x001C WDT_WIER 0x0000 0000 0x0000 0000
    0x0024 WDT_WCLR 0x0000 0020 0x0000 0024
    0x0028 WDT_WCRR 0x0000 0000 0x0000 0000
    0x002C WDT_WLDR 0x0000 0000 0xFFFF 4000
    0x0030 WDT_WTGR 0x0000 0000 0x0000 0000
    0x0034 WDT_WWPS 0x0000 0000 Read Only
    0x0044 WDT_WDLY 0x0000 0000 0x0000 0000
    0x0048 WDT_WSPR 0x0000 0000 0x0000 0000
    0x0054 WDT_WIRQSTATRAW 0x0000 0000 R/W1 to Set
    0x0058 WDT_WIRQSTAT 0x0000 0000 R/W1 to Clr
    0x005C WDT_WIRQENSET 0x0000 0000 R/W1 to Set
    0x0060 WDT_WIRQENCLR 0x0000 0000 R/W1 to Clr

    Regarding WDT_WCLR, when set at 10 or 20 seconds, the setting values are as follows.

    10 seconds: 0xFFFD 8000
    20 seconds: 0xFFFB 0000

    ======================================================================

    I am checking the value of CTRL_CLK32KDIVRATIO Register to my customer.
    If you need to check the other register value, please let me know.

    Best regards,
    Kanae

  • In reply to Kanae:

    Kanae

    Let me digest your input and get back to you, hopefully tomorrow. 

    --Paul 

  • In reply to PaulM:

    Hi Paul,

    I appreciate your continued support.

    Best regards,
    Kanae

  • In reply to Kanae:

    The settings you provided are valid for a 3s configuration. 

    Except for the WLDR register, are the same settings used for the 10s and 20s configurations?

    What method is used to turn off the LED, interrupt or reset? 

    Did you validate the 192MHz clock?

    Can you double check the PRCM_CM_DPLL_CLKSEL_WDT1_CLK  setting?

    --Paul 

  • In reply to PaulM:

    Hi Paul,

    Thank you for your reply.

    I will check my customer about your questions. 

    The value of CTRL_CLK32KDIVRATIO Register is "0x0",
    it sets the default (OPP100) value.

    Best regards,
    Kanae

  • In reply to Kanae:

    Hi Paul,

    Here are my customer's reply.

    =======================================================================

    The settings you provided are valid for a 3s configuration. 

    >What do you mean by "The settings you provided are valid for a 3s configuration"?

    Except for the WLDR register, are the same settings used for the 10s and 20s configurations?

    >I have not changed any registers other than the ones mentioned above.
      However, it has been a little while since I checked, so I will check again and let you know.

    What method is used to turn off the LED, interrupt or reset? 

    >The LEDs are turned on and off from the GPIO port.
    Power is supplied to the CPU, and as the application runs,
    the output of the IO port changes from '1' to '0' to '1' at regular intervals and blinks.
    WatcdogTimer is then enabled using serial debugging (UART) or ICE.
    When the WatcdogTimer is activated, the IO output stops and the LED turns off.
    The time from issuing the command to turning off the LED is measured with a stopwatch.

    Did you validate the 192MHz clock?

    >The 192MHz clock is generated by the PLL inside the CPU, and we are aware that it is used inside the IC.
    I haven't been able to confirm this yet because I don't have a way to measure the signal inside the IC.
    Can you please tell me how I can easily check this?

    Can you double check the PRCM_CM_DPLL_CLKSEL_WDT1_CLK  setting?

    >I will check the above register setting values during the operation check again and contact you.

    =======================================================================

    If you need to know other details, please let me know.

    Best regards,
    Kanae

  • In reply to Kanae:

    Kanae

    Hi Paul,

    Here are my customer's reply.

    =======================================================================

    The settings you provided are valid for a 3s configuration. 

    >What do you mean by "The settings you provided are valid for a 3s configuration"?

    The table of WDT register setting values you provided earlier equate to a 3 second timeout configuration. 

    From an earlier post...

    Kanae

    ========================================================
    The 32kHz clock that serves as the source is generated internally, 
    and the external XTAL is 24MHz.
    The oscillator for the RTC is not used.

    WDT Register setting values;

    0x0000 WDT_WIDR 0x0000 0000 Read Only
    0x0010 WDT_WDSC 0x0000 0010 0x0000 0010
    0x0014 WDT_WDST 0x0000 0001 Read Only
    0x0018 WDT_WISR 0x0000 0000 0x0000 0000
    0x001C WDT_WIER 0x0000 0000 0x0000 0000
    0x0024 WDT_WCLR 0x0000 0020 0x0000 0024
    0x0028 WDT_WCRR 0x0000 0000 0x0000 0000
    0x002C WDT_WLDR 0x0000 0000 0xFFFF 4000
    0x0030 WDT_WTGR 0x0000 0000 0x0000 0000
    0x0034 WDT_WWPS 0x0000 0000 Read Only
    0x0044 WDT_WDLY 0x0000 0000 0x0000 0000
    0x0048 WDT_WSPR 0x0000 0000 0x0000 0000
    0x0054 WDT_WIRQSTATRAW 0x0000 0000 R/W1 to Set
    0x0058 WDT_WIRQSTAT 0x0000 0000 R/W1 to Clr
    0x005C WDT_WIRQENSET 0x0000 0000 R/W1 to Set
    0x0060 WDT_WIRQENCLR 0x0000 0000 R/W1 to Clr

    Except for the WLDR register, are the same settings used for the 10s and 20s configurations?

    >I have not changed any registers other than the ones mentioned above.
      However, it has been a little while since I checked, so I will check again and let you know.

    Please do confirm that no other registers were updated other than the WLDR register for the 10s and 20s configurations 

    What method is used to turn off the LED, interrupt or reset? 

    >The LEDs are turned on and off from the GPIO port.
    Power is supplied to the CPU, and as the application runs,
    the output of the IO port changes from '1' to '0' to '1' at regular intervals and blinks.
    WatcdogTimer is then enabled using serial debugging (UART) or ICE.
    When the WatcdogTimer is activated, the IO output stops and the LED turns off.
    The time from issuing the command to turning off the LED is measured with a stopwatch.

    I am not clear on this methodology and still don't know if you are interrupting the software control of the LED or relaying on the generation of WARMRESET as a result of the WDT timeout.  If the later, than you will be able to monitor the warm reset signal (nRESETIN_OUT, ball G22) as a indication of the WDT timeout. 

    Did you validate the 192MHz clock?

    >The 192MHz clock is generated by the PLL inside the CPU, and we are aware that it is used inside the IC.
    I haven't been able to confirm this yet because I don't have a way to measure the signal inside the IC.
    Can you please tell me how I can easily check this?

    The 192Mhz clock can be monitored via the CLKOUT2 pin (C24).
    You will need to set the C24 pinmux to 0x3. Details on the register program can be found in the TRM, section 6.6.14 CLKOUT Signals

    If it is not possible to monitor the clock on ball C24, then we can review the PLL and clock settings

  • In reply to PaulM:

    Hi Paul,

    Thank you for your reply.
    I will share your comments to my customer.

    I appreciate your continued support.

    Best regards,
    Kanae

  • In reply to Kanae:


    Hi Paul,

    I would like to confirm the following about the clock setting and checking my customer asking.

    ========================================================================================
    It is difficult to monitor the clock with C24 because the relevant PAD is not used and is not pulled out with test pins, etc.

    Regarding the review of the PLL and clock settings, after checking, if the current settings are fine, can they be left as they are?

    Or is it better to set the frequency to the same frequency but change the combination of the frequency division ratio?

    ==========================================================================================


    The other items you asked are currently being checked.


    Best regards,
    Kanae