DRA829V: J721E: Programming the DPHY_RX_IF MMRs

Hi Ahsan Hessain,

We have a CSIRX driver in PDK, which takes care of configuring both of these modules, could you please refer/use this driver?

Rgds,

Brijesh

Hello Brijesh,

dphy driver is but a couple of tbit register configurations which doesn't explain anything. I do see dphy configuration being done in csi driver of pdk; however that or the TRM doesn't explain why PSM clock frequency divider needs to be 0x53, what's left and right lane band speed and in what configuration band gap timer value needs to be 0x14. Can you please let me know if these default configurations would work for my use case mentioned above?

Hello Ahsan,

I would suggest to use driver interface, i think the default configuration is for 1.5Gbps speed. You would require to change lane speed to 800Mbps. There is a driver interface for changing this. Can you please try using it?

Regards,

Brijesh

Brijesh,

I can set the left and right lane speeds to CSIRX_LANE_BAND_SPEED_720_TO_800_MBPS (0xD, which by the way isn't mentioned in the TRM) but what about the band gap timer and PSM clock frequency divider. It is like hit or miss without knowing what these values actually do, and thus not very helpful.

Hello Ahsan,

We have raised this issue to our team to include the details in the specs. We are working on it, it should be included in one of upcoming release of documents.

Regards,

Brijesh

Hello,

I've inferred that PSM is a fixed clock on the SoC and have done the configuration accordingly, so this would do for now.

There's another issue where TRM says DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT0 register settings are in MHz but RTOS calls the corresponding configuration value macros "Mbps".

1. Does that mean 1 bit per cycle? Isn't the DPHY clock supposed to be a DDR clock. Or does this configuration have no relation with the link frequency and deals with data rate only? (in which case the given unit in TRM needs an update as well)

2. Does this correspond to the overall pixel rate on the link? e.g. say we have 2 lane CSI configuration at 800 Mbps,should we select lane band speed configuration as CSIRX_LANE_BAND_SPEED_800_TO_880_MBPS or should we use CSIRX_LANE_BAND_SPEED_1500_TO_1750_MBPS?

Hello Ahsan,

No, it is not in terms of MHz, it is per lane speed in terms of bits per sec. So if your lane speed is 800Mbps, then should configure CSIRX_LANE_BAND_SPEED_800_TO_880_MBPS in TBIT0 register. 

Regards,

Brijesh

Hi,

What about 2 lane configuration?

Hello Ahsan,

This configure is for per lane speed,

does not mater whether it is 2 lane or 4 lane. 

Regards,

Brijesh