Dear Champs,
My customer is trying to upload bare metal FW on IPU using remoteproc in U-Boot by referring below,
but they have no idea how they can customize resource table for bare metal FW(w/o ti-rtos) and found below log when they tried it.
~~~~~~~~~~~~~~
[ipu_rproc.c:ipu_probe:835] ID 0 memory l2ram: bus addr 0x58820000 size 0x10000 va 58820000 da 0x0
[ipu_rproc.c:ipu_probe:843] Load F/W: (dra7-ipu1-fw.xem4)
[ipu_rproc.c:load_firmware:755] F/W Name: (dra7-ipu1-fw.xem4)
[fs_loader.c:fw_get_filesystem_firmware:211] Trying to fs_read: (dra7-ipu1-fw.xem4)
[fs_loader.c:fw_get_filesystem_firmware:227] Success to read file... ret(0), actread(1377840)
[ipu_rproc.c:load_firmware:761] F/W Size: (1377840)
[ipu_rproc.c:spl_pre_boot_core:696] Trying to fine resource_table... CoreID(0)
[rproc-uclass.c:rproc_find_resource_table:974] failed to get resource section header
[rproc-uclass.c:rproc_find_resource_table:974] failed to get resource section header
[rproc-uclass.c:rproc_parse_resource_table:999] failed to find resource table...
[ipu_rproc.c:spl_pre_boot_core:734] load_elf_image_phdr returned error for core IPU1
[ipu_rproc.c:ipu_probe:858] Failed to SPL Pre-boot Core (0)
Their cmd file is as below.
/****************************************************************************/
/* AM57xx_CM4.cmd */
/* Copyright (c) 2015 Texas Instruments Incorporated */
/* Author: Rafael de Souza */
/* */
/* Description: This file is a sample linker command file that can be */
/* used for linking programs built with the C compiler and */
/* running the resulting .out file on the Cortex M4 core of */
/* an AM57xx device. */
/* Use it as a guideline. You will want to */
/* change the memory layout to match your specific */
/* target system. You may want to change the allocation */
/* scheme according to the size of your program. */
/* */
/****************************************************************************/
--retain='*(.intvecs)'
--retain='*(.intc_text)'
#ifdef MMU /* memory map with MMU turned on */
MEMORY
{
IRAM: o = 0x00000000 l = 0x00001000 /* 4kB internal SRAM */
OCMC_RAM1: o = 0x00300000 l = 0x00080000 /* 512k L3 OCMC SRAM1 */
OCMC_RAM2: o = 0x00400000 l = 0x00100000 /* 1MB L3 OCMC SRAM2 */
OCMC_RAM3: o = 0x00500000 l = 0x00100000 /* 1MB L3 OCMC SRAM3 */
DDR0: o = 0x80000000 l = 0x3FFF0000 /* 1GB external DDR Bank 0 */
DDR0_DEBUG o = 0xBFFF0000 l = 0x00010000 /* 64K DDR DEBUG */
OCMC_EDMA: o = 0x40500000 l = 0x00100000 /* 1MB L3 OCMC SRAM3 EDMA*/
}
#else /* memory map with MMU turned off */
MEMORY
{
IRAM: o = 0x00000000 l = 0x00001000 /* 4kB internal SRAM */
OCMC_RAM1: o = 0x40300000 l = 0x00080000 /* 512kB L3 OCMC SRAM1 */
OCMC_RAM2: o = 0x40400000 l = 0x00100000 /* 1MB L3 OCMC SRAM2 */
OCMC_RAM3: o = 0x40500000 l = 0x00100000 /* 1MB L3 OCMC SRAM3 */
DDR0: o = 0x80000000 l = 0x40000000 /* 1GB external DDR Bank 0 */
}
#endif
SECTIONS
{
.intvecs: > 0x00000000
.intc_text: > IRAM
.text: > OCMC_RAM1
.const: > OCMC_RAM1
.cinit: > OCMC_RAM1
.init_array: > OCMC_RAM1
.data: > OCMC_RAM1
.bss: > OCMC_RAM1
.stack: > OCMC_RAM1
.sysmem: > OCMC_RAM1
// .my_sect_ddr > DDR0
// .dbug_cmd > DDR0_DEBUG
}
Could you please guide how they can customize resource table for their baremetal FW?
Are there specific things in resource table for baremetal FW?
Thanks and Best Regards,
SI.
