• State Resolved
  • Locked Locked
  • Replies 14 replies
  • Answers 2 answers
  • Subscribers 102 subscribers
  • Views 346 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA2P-ACD: CSI-2 RX maximum frequency

Vicent Climent14
Intellectual 360 points
Part Number: TDA2P-ACD

Dear TI team, 

We have a TDA2p connected to a DS90UB954 deser. 

The CSI-2 interface (4data + 1clk) is running with a CSI_CLK of 800MHz and it is working just fine. However, we have recently seen in the datasheet (SPRS996F –MARCH 2017–REVISED FEBRUARY 2019 - Section 6.15.14.1) that the MIPI D-PHY RX spec for the TDA2p is 1.5Gbps per lane (750MHz).

Is the spec for the TDA2p correct? Or is 800MHz supported?

BR,

Vicent Climent.

  • 0
    TI__Guru**** 398170 points

    Hi Vincent,

    TRM is correct. Which device are you using for 800MHz output?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 360 points

    Hi Brijesh,

    We are using a deserializer as CSI output, from TI too. DS90UB954

    BR,

    Vicent.

  • 0 in reply to Vicent Climent14
    TI__Guru**** 398170 points

    Hi Vincent,

    What is the resolution that you are transmitting from the sensor? I think all together transfer rate will be less than 1.5Gbps per lane.  

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 360 points

    Hello Brijesh,

    We are actually in the range of 1.2Gbps per lane. So we have some room to reduce the speed. 

    However, as we have not detected any functional problems, I wanted to check with you if this 800MHz would be acceptable for the TDA2p, as changing this frequency could impact on our EMC performance. 

    BR,

    Vicent.

  • 0 in reply to Vicent Climent14
    TI__Guru**** 398170 points

    Hi Vincent,

    We also have not seen any problem in using this frequency. I will still check with out HW expert and get back to you.

    Also please note that if I remember correctly, ub960 output speed depends on the reference input clock. So are you sure it is 800MHz?

    Rgds,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 360 points

    Hi Brijesh,

    We have measured this and we get 800MHz almost exactly. We are using a 25MHz clock. The part we are using to interface with TDA2p is the ub954, so maybe that is where the confusion is coming?

    BR,

    Vicent

  • 0 in reply to Vicent Climent14
    TI__Guru**** 398170 points

    Hi Vincent,

    The max lane speed support is 1.5 Gbps.  1.6 Gbps may work but is not officially supported.

    I would also suggest you to go through errata i904 to make sure setup and hold timings are correct for 1.5Gbps lane speed. 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 360 points

    Hi Brijesh, 

    I went through errata i904. But I am not able to find any concrete values for setup and hold timings.

    • Do you have this information so that I can compare the measurements?
    • Errata i904 I was reviewing was actually referring to >1.2Gbps. If we fulfill the requirement for >1.2Gbps, then is it safe to say that our current 1.6Gbps are okay?

    This was the document that I was reviewing:

    www.ti.com/.../sprz454.pdf

    BR,

    Vicent

  • 0 in reply to Vicent Climent14
    TI__Guru**** 398170 points

    Hi Vicent,

    We are checking with our HW team and will get back as soon as possible.

    Regards,

    Brijesh 

  • 0 in reply to Vicent Climent14
    TI__Genius 10180 points

    Vicent,

    If the device can provide 166 ps setup/hold time at 1.5 Gbps then it will be compatible with TDA2Px. 

    Even if higher speed meets this criteria, 1.5 Gbps is still the maximum supported data rate.

    Thanks & Regards,

    Shiou Mei

  • 0 in reply to Shiou Mei Huang
    Intellectual 360 points

    Hello Shiou Mei, 

    Thanks for your comments. 

    • What would be the risks in case that we meet the setup/hold time criteria but still we keep the 1.6Gbps maximum data rate?

    This is important to us because after digging further in the DS90UB954 we have found that it is only able to set 3 different data rates. Due to the amount of data that we handle, we can only use the fastest 1.6Gbps. It looks like the only way that we have to properly adjust it is by changing the DS90UB954 reference oscillator, from 25MHz to 23MHz. We'd like to avoid this due to the implications that this may have at this stage of the project. 

    Regards,

    Vicent 

  • 0 in reply to Vicent Climent14
    TI__Genius 10180 points

    Vicent,

    Apologies for the delay.  The buffer is rated for 1.5 Gbps; any overclocking may result in reliability concerns and not guaranteed for operation.  DS90UB954 supports 1.5 Gbps data rate operation and yes you are correct the REFCLK will have to change to 23 MHz.   Quoting the DS90UB954 datasheet:

    In the case of alternate settings, the respective CSI-2 timing parameters registers must be programmed, and the appropriate override bit must be set. For the 1.664-Gbps and 1.472-Gbps options, these settings will also affect internal device timing for back channel operation, I2C, Bidirectional Control Channel, and FrameSync operation which scale with the REFCLK frequency. 

    Please let me know if you have additional questions.

    Best Regards,

    Shiou Mei

     

  • 0 in reply to Shiou Mei Huang
    Intellectual 360 points

    Hello Shiou Mei,

    My first guess was that we might be experiencing some CRC issues due to the hold/set-up time limitation described in errata i904. That we could maybe just skip some good bits during the transmission. 

    Your explanation seems to go much deeper than that. Do your have further information with regards to which "reliability concerns and not guaranteed for operation"?

    Regards,

    Vicent.

  • 0 in reply to Vicent Climent14
    TI__Genius 10180 points

    Vincent,

    By "reliability concerns", I meant the interface is not guaranteed to function correctly if operated outside of the datasheet specifications.  If the interface is overclocked, the interface may not meet the target bit-error-rate (BER) as specified in the MIPI D-PHY specifications.

    Best Regards,

    Shiou Mei