DRA821U: serdes_wiz configuration

Hi,

Can you provide more details ? What are you looking at ? Driver, App etc

Please point to the exact piece of code/configuration/documentation.

Regards

Vineet

Hello Vineet,

thanks for your reply!

I was comparing the following device trees.

k3-j7200-common-proc-board.dts

&serdes_wiz0 {
    status = "disabled";
};

k3-j721e-main.dtsi

serdes_wiz0: wiz@5000000 {
        compatible = "ti,j721e-wiz-16g";
        #address-cells = <1>;
        #size-cells = <1>;
        power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
        clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
        clock-names = "fck", "core_ref_clk", "ext_ref_clk";
        assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
        assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
        num-lanes = <2>;
        #reset-cells = <1>;
        ranges = <0x5000000 0x0 0x5000000 0x10000>;

...

I was wondering about what is the proper configuration for the serdes interface and what this sederes_wiz configuration is excactly doing?

We want connect with SGMII to the switch.

Best regards

Janis

Hi Janis,

Sorry for the delay, I acknowledge your reply and wanted to let you know that we are looking at this issue. I will get back on this within a day or two.

Regards

Vineet

Hi Janis,

If you are looking at enabling SGMII then take a look at this reference patch for DRA829

Generally speaking, you only need to disable the SERDES configuration from Linux and enable it in EthFW on MCU 2_0 since there is a conflict in SERDES and all PHY configuration must be done from EthFW.

For an explanation on SERDES WIZ, see this, it's only a wrapper for SERDES configuration. For an explanation on the parameters, please check this documentation

Regards

Vineet

Hi Vineet,

thanks for your reply!

I'm unfortunately not able to open the link regarding the reference patch.

This means basically, for bringing up eth-communication via SGMII the linux-kernel running on A72 cores is not involved?

But there is a way to share eth communication between the EthFw and the linux-system or?

I found this kind of configuration in the device tree from what I thought it's for this use case:

cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
        compatible = "ti,j721e-cpsw-virt-mac";
        dma-coherent;
        ti,psil-base = <0x4a00>;
        ti,remote-name = "mpu_1_0_ethswitch-device-0";

        dmas = <&main_udmap 0xca00>,
               <&main_udmap 0xca01>,
               <&main_udmap 0xca02>,
               <&main_udmap 0xca03>,
               <&main_udmap 0xca04>,
               <&main_udmap 0xca05>,
               <&main_udmap 0xca06>,
               <&main_udmap 0xca07>,
               <&main_udmap 0x4a00>;
        dma-names = "tx0", "tx1", "tx2", "tx3",
                "tx4", "tx5", "tx6", "tx7",
                "rx";

        virt_emac_port {
            ti,label = "virt-port";
            /* local-mac-address = [0 0 0 0 0 0]; */
        };
    };

Best regards

Janis

Hi Janis,

Sorry, it was an internal link. I am now attaching the relevant files here.

The guide for enabling SGMII patch is here

Enable8PortEth_J7EVM_SDK7p1_public.pdf

The patches are here

ethfw_qsgmii_sdk7p1(1).zip

>>This means basically, for bringing up eth-communication via SGMII the linux-kernel running on A72 cores is not involved?

That's right

>> But there is a way to share eth communication between the EthFw and the linux-system or?

EthFw brings up the CPSW switch and has complete control of the IP but the traffic can be routed internally from the switch to any core (even A72 running Linux). EthFW is not involved in that.

You can take a look at this documentation

Regards

Vineet